Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a D.sub.it of about 5e.sup.10 cm.sup.−2eV.sup.−1 to about 5e.sup.11 cm.sup.−2eV.sup.−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

The invention relates to a method for manufacturing an electronic device, particularly a device including a flexible and/or low-cost substrate and/or carbon nanotubes, and also relates to electronic devices produced using said method. The method for manufacturing an electronic device, including a substrate mad of a material M and an active semiconductor material layer (3), includes the following steps: a) providing a carrier (10) made of an alkali metal salt or alkaline earth metal salt, preferably sodium chloride (NaCl) or potassium chloride (KCl); optionally, b) depositing a dielectric material layer (2) onto one surface of the carrier; c) forming an active semiconductor material layer (3) on one surface of the carrier when Step b) is not implemented or on the free surface of the layer when Step b) is implemented; d) forming different components of the electronic device on and/or under the layer; e) depositing a protective layer onto the layer stack, obtained in Step d), of the different components of the electronic device, said protective layer being made of the material M required for the substrate (1); and f) removing the carrier (10) by dissolving one or more of the components of said electronic device on a substrate different from the substrate (1). In said removal of the carrier, the method does not include any step for manufacturing one or more of the components of said electronic device on a substrate different from the substrate (1). The invention is of use in the field of electronics in particular.

An organic transistor including at least one lower substrate made of plastic material, two electrodes, respectively a source electrode and a drain electrode, deposited on the plastic substrate, a semiconductor layer made of an organic semiconductor material and deposited on the electrodes and the plastic substrate, a dielectric layer deposited on the semiconductor layer, and a gate electrode formed on said dielectric layer. It further includes a porous layer extending between the plastic substrate and the semiconductor layer, said porous layer extending at least between the source and drain electrodes, to decrease the dielectric constant of the surface of said plastic substrate.

A solid or quasisolid state hole transport material (HTM) includes the following complex:

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in which M is copper (Cu), palladium (Pd), gold (Au), silver (Ag), nickel (Ni), vanadium (V) cobalt (Co); and each structure represents an at least 6,6′ disubstituted 2,2′-bipyridine, or an at least 2,9 disubstituted 1,10-phenanthroline Electronic devices, such as solar cells can include the solid or quasisolid state HTM, in which the complex is the main hole conducting compound of the HTM.

The present teachings relate to compositions for forming a negative-tone photopatternable dielectric material, where the compositions include, among other components, an organic filler and one or more photoactive compounds, and where the presence of the organic filler enables the effective removal of such photoactive compounds (after curing, and during or after the development step) which, if allowed to remain in the photopatterned dielectric material, would lead to deleterious effects on its dielectric properties.

Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.

High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (FETs) that incorporate the films as conducting channel materials. The single-walled carbon nanotubes are deposited from a thin layer of organic solvent containing solubilized single-walled carbon nanotubes that is spread over the surface of an aqueous medium, inducing evaporative self-assembly upon contacting a solid substrate.

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Novel compounds useful as organic semiconductor material are described. Semiconductor devices containing said organic semiconductor material are also described.