A display panel includes: a substrate including a first display area, a second display area, and a peripheral area; a first pixel circuit at the first display area and a first display element connected to the first pixel circuit; a second display element at the second display area; a second pixel circuit at on the peripheral area; a connection line between the substrate and the second display element and connecting the second display element to the second pixel circuit; and a connection portion on a different layer from the connection line and connected to the second display element, wherein the second display element includes a second pixel electrode, wherein the second pixel electrode is on a same layer as the connection portion and covers at least a portion of the connection portion.

The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a first electrode layer on the base substrate and including a plurality of first electrodes respectively in the plurality of subpixel areas; an auxiliary electrode layer; and an insulating layer between the first electrode layer and the auxiliary electrode layer. The first electrode layer and the auxiliary electrode layer are spaced apart and insulated from each other by the insulating layer. An orthographic projection of each individual one of the plurality of first electrodes on the base substrate at least partially overlap with an orthographic projection of the auxiliary electrode layer on the base substrate. Each of the plurality of first electrodes is electrically connected to a pixel circuit configured to drive light emission in a respective one of the plurality of subpixel areas.

An organic light emitting display (OLED) device includes a substrate, a semiconductor element on the substrate, a planarization layer on the semiconductor, and a light emitting structure on the planarization layer. The planarization layer includes a contact hole exposing a portion of the semiconductor and a plurality of grooves surrounding the contact hole. The light emitting structure is electrically connected to the semiconductor element via the contact hole.

The present invention provides a display device, including a display panel and an encapsulation cover disposed on the display panel. Two circles of border sealant are sequentially disposed at intervals between the bonding area of the encapsulation cover and the display panel from periphery to the inside. The invention provides a display device, which adopts a novel encapsulation structure so that it can effectively prevent external water and oxygen from invading into the internal display panel, and therefore improve its own stability.

A display device can include a thin-film transistor (TFT) and an auxiliary electrode disposed on a substrate and spaced apart from each other, a passivation layer disposed on the TFT and the auxiliary electrode, a first barrier rib and a second barrier rib disposed on the passivation layer and spaced apart from each other, a first electrode disposed on the first barrier rib and connected to the TFT, a connecting electrode disposed on the second barrier rib and connected to the auxiliary electrode, a bank layer disposed on the passivation layer and including a first opening exposing a portion of the first electrode and a second opening exposing a portion of the connecting electrode, an organic emitting layer disposed on the first electrode and separated by the second barrier rib, and a second electrode disposed on the organic emitting layer and contacting the connecting electrode near the second barrier rib.

In some embodiments, the present disclosure relates to a display device. The display device includes an isolation structure disposed over a reflector electrode, an additional electrode disposed over the isolation structure, and an optical emitter structure disposed over the additional electrode. A via structure includes a lower horizontal segment disposed on the reflector electrode, a vertical segment extending along a sidewall of the isolation structure, and an upper horizontal segment disposed over the isolation structure. The upper horizontal segment is connected to the lower horizontal segment by the vertical segment.

A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

A display device includes an opening area formed in a display area and a non-display area surrounding the opening area, wherein the display area includes a plurality of pixels and a plurality of lines connected to the plurality of pixels, the non-display area includes a connection member connected to at least one of the plurality of lines of the display area, and the connection member is disposed in a different layer from the connected line and is electrically connected to the line by a via-electrode.

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.