Patent classifications
H10K59/124
Array substrate, manufacturing method thereof, display panel and display device
An array substrate is provided, including a base substrate, a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode that are sequentially provided, and further including a first insulating layer, a second insulating layer, a third insulating layer, at least one first via, and at least one second via. Each first via penetrates through the third insulating layer, and in each pixel unit with plural chromatic color resists, each first via is between adjacent two chromatic color resists and filled by one of the adjacent two chromatic color resists. Each second via penetrates through the second insulating layer, the at least one second via is in one-to-one correspondence with the at least one first via, each second via is filled by a chromatic color resist having a same color as that of the chromatic color resist in the corresponding first via.
Method of fabricating a display apparatus
A display apparatus may include a base substrate including a first portion and a second portion smaller than the first portion, a plurality of pixels disposed on the first portion, a protection substrate disposed below the base substrate, and a groove disposed in a portion of the protection substrate and overlapped with the second portion. The groove may include a first region extending in a first direction, and a second region and a third region, which are arranged along the first direction, wherein the first region is interposed between the second region and the third region. The first and second portions may be arranged in a second direction crossing the first direction, and a width of each of the second and third regions may be larger than a first width of the first region, when measured in the second direction.
Array substrate and method for manufacturing the same, method and assembly for detecting light, and display device
An array substrate and a method for manufacturing the same, a method and assembly for detecting light, and a display device are provided. The array substrate includes: a base substrate having a pixel region; a light detecting unit, a switch unit, and a light emitting unit that are located in the pixel region, where the light emitting unit and the light detecting unit share the switch unit.
Pixel circuit and display device including the same
A pixel circuit includes first to fifth transistors, a capacitor, and a light emitting element. The first transistor is coupled between first and second power lines, and includes a gate electrode coupled to a first node and a back-gate electrode coupled to a second node. The second transistor is coupled between a data line and the first node, and includes a gate electrode coupled to a first scan line. The third transistor is coupled between a third power line and the first node, and includes a gate electrode coupled to a reference scan line. The fourth transistor is coupled between a second node and a fourth power line, and includes a gate electrode coupled to a second scan line. The fifth transistor is coupled between a first power line and the one electrode of the first transistor, and includes a gate electrode coupled to a light-emitting control line.
Display device
A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.
Display device including light-emitting portions having opposing angle directions
A display device includes a display panel having first and second regions with the second region having a higher resolution than the first region and an electronic module under the first region. The display panel includes first and second emission layers in a first sub-region of the first region with the second emission layer being spaced apart from the first emission layer. The first emission layer has a first light-emitting portion and a second light-emitting portion adjacent to the first light-emitting portion in a first direction, and the second emission layer has a third light-emitting portion and a fourth light-emitting portion adjacent to the third light-emitting portion in the first direction. The first light-emitting portion is inclined from the second light-emitting portion toward a lower surface of the display panel, and the fourth light-emitting portion is inclined from the third light-emitting portion toward an upper surface of the display panel.
Display apparatus including multi-layered planarization layer
A display apparatus includes: a substrate having a display area and a peripheral area outside the display area; a first conductive layer on the substrate in the peripheral area and comprising a first hole; a second conductive layer on the first conductive layer and overlapping the first conductive layer, the second conductive layer comprising a second hole; a planarization layer extending from the display area to the peripheral area and comprising at least two organic insulating layers between the first conductive layer and the second conductive layer; and a display element on the planarization layer in the display area, wherein a part of a portion of the second conductive layer except for the second hole is in contact with a part of a portion of the first conductive layer except for the first hole.
Display panel including dam and recess, and display apparatus including the same
A display panel includes: a substrate including an opening area, a display area, and a non-display area, the display area surrounding the opening area, and the non-display area being between the opening area and the display area; a plurality of display elements at the display area of the substrate, each of the display elements including a pixel electrode, an emission layer on the pixel electrode, and an opposite electrode on the emission layer; a thin-film encapsulation layer covering the plurality of display elements; a dam at the non-display area, and protruding from a top surface of a first insulating layer; and a recess between the opening area and the dam, and recessed in a depth direction of the first insulating layer. A lateral wall of the dam meets a first lateral wall from among lateral walls of the recess, the first lateral wall being adjacent to the display area.
Display device with bottom conductive pattern and method of manufacturing the same
A display device includes a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom surface, the bottom planarization layer disposed on the bottom conductive pattern.
Display panel and display apparatus including the same
A display panel includes a 1-1.sup.st sub-pixel and a 1-2nd sub-pixel disposed in a first row, a 2-1.sup.st sub-pixel disposed in a second row and a 3-1.sup.st sub-pixel and a 3-2nd sub-pixel disposed in a third row. A first data line extends from the first row to the third row and electrically connects a pixel circuit of the 1-1.sup.st sub-pixel, a pixel circuit of the 2-1.sup.st sub-pixel, and a pixel circuit of the 3-1.sup.st sub-pixel. A 2-1.sup.st data line is electrically connected to a pixel circuit of the 1-2nd sub-pixel. A 2-2nd data line is electrically connected to a pixel circuit of the 3-2nd sub-pixel. A first bridge line is disposed on a different layer than the data lines and contacts the 2-1.sup.st data line and the 2-2nd data line and includes an overlapping portion extending along at least a portion of the first data line.