Patent classifications
H10K71/233
Method for manufacturing an organic electronic device and organic electronic device
The disclosure provides a method of manufacturing an organic electronic device, including providing a layered device structure, the layered device structure including a plurality of electrodes and an electronically active region, said providing of the layered device structure including steps of providing an organic semiconducting layer, applying a structuring layer to the organic semiconducting layer, the structuring layer having a first region and a second region, the first region being covered by a layer material, applying a contact improving layer to the structuring layer by depositing at least one of an organic dopant material and an organic dopant-matrix material at least in the first region, depositing a layer material on the contact improving layer at least in the first region, and removing the structuring layer at least in the second region. Furthermore, an organic electronic device is provided.
Display substrate, method of manufacturing display substrate, and display device including display substrate
A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.
Display device and method of fabricating the same
A display device includes a planarization layer disposed on a substrate, a first electrode disposed on the planarization layer and including silver (Ag), a contact preventing layer disposed on the first electrode, including a light absorbing material, and including a top surface and a side surface extending from an end of the top surface, and a pixel defining layer disposed on the contact preventing layer and including a bottom surface facing the top surface of the contact preventing layer, and a side surface extending from an end of the bottom surface. The first electrode includes a first region overlapping pixel defining layer. The contact preventing layer includes a second region overlapping the first region between the first electrode and the pixel defining layer. A first edge where the top and side surfaces of the contact preventing layer meet is located on the bottom surface of the pixel defining layer.
ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
An organic light-emitting display apparatus includes: first and second pixel electrodes on a substrate, and spaced from each other; a pixel-defining film surrounding edges of the first and second pixel electrodes; a first intermediate layer on the first pixel electrode; a second intermediate layer on the second pixel electrode, spaced from the first intermediate layer; a first counter electrode on the first intermediate layer; a second counter electrode on the second intermediate layer, spaced from the first counter electrode; a first passivation layer on the first counter electrode; a second passivation layer on the second counter electrode, spaced from the first passivation layer; a first bank around the first passivation layer and protruding from the pixel-defining film to extend in a direction away from the substrate; and a second bank around the second passivation layer and protruding from the pixel-defining film to extend in the direction away from the substrate.
METHOD FOR MANUFACTURING HIGH-DENSITY ORGANIC MEMORY DEVICE
A method for manufacturing an organic memory device is disclosed. According to one embodiment, the method comprises the steps of: forming a first electrode on a substrate; forming an organic active layer on the first electrode; and forming a second electrode on the organic active layer through an orthogonal photolithography technique using a fluorinated material.
Patterning devices using fluorinated compounds
A method for producing a spatially patterned structure includes forming a layer of a material on at least a portion of a substructure of the spatially patterned structure, forming a barrier layer of a fluorinated material on the layer of material to provide an intermediate structure, and exposing the intermediate structure to at least one of a second material or radiation to cause at least one of a chemical change or a structural change to at least a portion of the intermediate structure. The barrier layer substantially protects the layer of the material from chemical and structural changes during the exposing. Substructures are produced according to this method.
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A display device includes a substrate, an active pattern disposed on the substrate, a gate electrode overlapping the active pattern, an inorganic insulation layer covering the active pattern, a source metal pattern and an etch-delaying pattern. The source metal pattern includes a first portion that is disposed on the inorganic insulation layer, and a second portion that passes through the inorganic insulation layer and electrically contacts the active pattern. The etch-delaying pattern is disposed between the active pattern and the first portion of the source metal pattern, contacts the second portion of the source metal pattern, and includes a different material from the inorganic insulation layer.
Nanoparticle, method for preparing display substrate and display device
The nanoparticle of the embodiments of the present disclosure includes nanograins, and a first ligand and a second ligand connected to a surface of each nanograin, wherein the first ligand has alkali solubility, and the second ligand undergoes a crosslinking reaction when heated. The method for preparing the display substrate according to embodiments of the present disclosure includes: forming a nanoparticle layer on a substrate; coating a photoresist on the nanoparticle layer, exposing the photoresist with a mask; developing to remove the photoresist in the photoresist removal region, such that the exposed nanoparticle layer is dissolved into a developing solution; performing post-baking treatment, such that a second ligand of the nanoparticle covered by the photoresist in the photoresist reserved region undergoes a crosslinking reaction, and the nanoparticle layer covered by the photoresist in the photoresist reserved region is fixed on the substrate; and stripping the photoresist, to complete a patterning of the nanoparticle layer.
Self aligned pattern formation post spacer etchback in tight pitch configurations
A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR USING CARBON NANOTUBES AND A FIELD EFFECT TRANSISTOR
In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.