A piezoelectric device and method of manufacturing the same and an inkjet head are described. In one embodiment, the inkjet print head comprises a plurality of jets, wherein each of the plurality of jets comprises a nozzle, a pressure chamber connected with the nozzle, a piezoelectric body coupled to the pressure chamber, and an electrode coupled to the piezoelectric body to cause displacement of the piezoelectric body to apply pressure to the pressure chamber in response to a voltage applied to the electrode; and wherein electrodes of two or more of the plurality of jets have different sizes to cause their associated piezoelectric bodies to have a uniform displacement amount when the voltage is applied to the electrodes.

The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method. The gate structure according to the invention comprises a substrate; a piezoelectric active layer (112, 212) disposed on the substrate (110, 210); a passivation layer (120, 220) disposed on the active layer (112, 212), wherein the passivation layer (120, 220) has a recess (122, 222) that extends through the entire passivation layer (120, 220) in the direction of the active layer (112, 212); a contact element (140, 240) disposed within the recess (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); and a cover layer (150, 250) that covers the contact element (140, 240) above the passivation layer (120, 220); wherein at least one layer disposed above the active layer is tensile stressed or compressively stressed in the area around the contact element, with a normal tension of ||>200 MPa, wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element.

The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method. The gate structure according to the invention comprises a substrate; a piezoelectric active layer (112, 212) disposed on the substrate (110, 210); a passivation layer (120, 220) disposed on the active layer (112, 212), wherein the passivation layer (120, 220) has a recess (122, 222) that extends through the entire passivation layer (120, 220) in the direction of the active layer (112, 212); a contact element (140, 240) disposed within the recess (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); and a cover layer (150, 250) that covers the contact element (140, 240) above the passivation layer (120, 220); wherein at least one layer disposed above the active layer is tensile stressed or compressively stressed in the area around the contact element, with a normal tension of ||>200 MPa, wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element.

Even with the occurrence of misalignment of inner electrodes in a ceramic collective board, a multilayer electronic component is made in which inner electrodes are disposed at suitable positions. Disclosed herein are descriptions of a first-stage ceramic collective board and a second-stage ceramic collective board used for manufacturing a multilayer electronic component. The present disclosure further describes a manufacturing method for the second-stage ceramic collective board and a manufacturing method for a multilayer electronic component.

There is provided a piezoelectric stack including: a substrate (1); a bottom electrode film (2) on the substrate; a piezoelectric film (3) on the bottom electrode film, having a planar area smaller than a planar area of the bottom electrode film; a top electrode film (4) on the piezoelectric film; and an insulating film (5) provided from the top electrode film to the bottom electrode film and covering at least a part of a side surface of the piezoelectric film, wherein the insulating film has a slope (9a) filling a step between a top surface of the top electrode film and a top surface of the bottom electrode film, and the slope has a shape alleviating the step.

There is provided a piezoelectric stack including: a substrate (1); a bottom electrode film (2) on the substrate; a piezoelectric film (3) on the bottom electrode film, having a planar area smaller than a planar area of the bottom electrode film; a top electrode film (4) on the piezoelectric film; and an insulating film (5) provided from the top electrode film to the bottom electrode film and covering at least a part of a side surface of the piezoelectric film, wherein the insulating film has a slope (9a) filling a step between a top surface of the top electrode film and a top surface of the bottom electrode film, and the slope has a shape alleviating the step.

An electronic device package comprises an electrical device disposed on a base substrate, a conductive column in electrical communication with the electrical device and having a first end bonded to the base substrate, a cap substrate disposed over the electrical device and bonded to a second end of the conductive column, a layer of organic dielectric buffer coat material on the lower surface of the base substrate, a through substrate via in electrical communication with the conductive column and passing through the base substrate and the layer of organic dielectric buffer coat material, a redistribution layer disposed on the layer of organic dielectric buffer coat material, and a contact pad formed on the redistribution layer and in electrical communication with the through substrate via through the redistribution layer, the contact pad being horizontally displaced from a position directly below the through substrate via.

An electronic device package comprises an electrical device disposed on a base substrate, a conductive column in electrical communication with the electrical device and having a first end bonded to the base substrate, a cap substrate disposed over the electrical device and bonded to a second end of the conductive column, a layer of organic dielectric buffer coat material on the lower surface of the base substrate, a through substrate via in electrical communication with the conductive column and passing through the base substrate and the layer of organic dielectric buffer coat material, a redistribution layer disposed on the layer of organic dielectric buffer coat material, and a contact pad formed on the redistribution layer and in electrical communication with the through substrate via through the redistribution layer, the contact pad being horizontally displaced from a position directly below the through substrate via.

A device and a method are disclosed. In an embodiment, a device includes an oscillating body on which a piezoelectric element is fixed by a solder joint.

A device and a method are disclosed. In an embodiment, a device includes an oscillating body on which a piezoelectric element is fixed by a solder joint.