An electronic component includes external electrodes formed on an external surface of a body to be electrically connected to internal electrodes, and containing metal particles and glass, wherein the metal particles include particles having a polyhedral shape.

A multi-layer piezoelectric microactuator assembly has at least one poled and active piezoelectric layer and one poled but inactive piezoelectric layer. The poled but inactive layer acts as a constraining layer in resisting expansion or contract of the first piezoelectric layer.

According to one embodiment, a liquid discharge head includes a flexible printed circuit (FPC) connected to piezoelectric elements. The FPC has a first end in the first direction. A wiring layer of the FPC has a first region at the first end and a cover layer covering on a second region. The piezoelectric elements are spaced from each other in a second direction and each has a first electrode on a side surface facing towards the FPC. The first side has a joint surface facing the first region of the wiring layer. The first electrode is electrically connected to the wiring layer at the joint surface. The side surface includes a step portion that is recessed from the joint surface. A portion of the cover layer protrudes into a space adjacent to the step portion.

According to one embodiment, a liquid discharge head includes a flexible printed circuit (FPC) connected to piezoelectric elements. The FPC has a first end in the first direction. A wiring layer of the FPC has a first region at the first end and a cover layer covering on a second region. The piezoelectric elements are spaced from each other in a second direction and each has a first electrode on a side surface facing towards the FPC. The first side has a joint surface facing the first region of the wiring layer. The first electrode is electrically connected to the wiring layer at the joint surface. The side surface includes a step portion that is recessed from the joint surface. A portion of the cover layer protrudes into a space adjacent to the step portion.

The disclosed technology features methods for the manufacture of electrical components such as ultrasound transducers. In particular, the disclosed technology provides methods of creating an ultrasonic transducer by connecting one or more multi-layer printed circuits to an array of ultrasound transducer elements. In one embodiment, the printed circuits have traces in a single layer that are spaced by a distance that is greater than a pitch of the transducer elements to which the multi-layer printed circuit is to be connected. However the traces from all the layers in the multi-layer printed circuit are interleaved to have a pitch that is equal to the pitch of the transducer elements. The disclosed technology also features ultrasound transducers produced by the methods described herein.

The disclosed technology features methods for the manufacture of electrical components such as ultrasound transducers. In particular, the disclosed technology provides methods of creating an ultrasonic transducer by connecting one or more multi-layer printed circuits to an array of ultrasound transducer elements. In one embodiment, the printed circuits have traces in a single layer that are spaced by a distance that is greater than a pitch of the transducer elements to which the multi-layer printed circuit is to be connected. However the traces from all the layers in the multi-layer printed circuit are interleaved to have a pitch that is equal to the pitch of the transducer elements. The disclosed technology also features ultrasound transducers produced by the methods described herein.

Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

An electromechanical device comprising: first and second electrodes each comprising a metal layer; an active layer comprising at least one ferroelectric polymer and disposed between the first and the second electrode. The first electrode and the second electrode each comprise an interface layer comprising poly(3,4-ethylenedioxythiophene). Each interface layer is interposed between the active layer and the corresponding metal layer. The invention further relates to a method for manufacturing such a device.

An electroactive device may include a primary electrode, a secondary electrode overlapping at least a portion of the primary electrode, and a tertiary electrode overlapping at least a portion of the secondary electrode. The electroactive device may also include (i) a first electroactive polymer element including a first elastomer material disposed between and abutting the primary electrode and the secondary electrode, and (ii) a second electroactive polymer element including a second elastomer material disposed between and abutting the secondary electrode and the tertiary electrode. Various other devices, methods, and systems are also disclosed.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first piezoelectric layer, and a first dummy layer. The first piezoelectric layer is over the substrate, and the first piezoelectric layer has a first top surface. The first dummy layer is over the first piezoelectric layer, and the first dummy layer has a second top surface. And an average roughness of the first top surface is greater than an average roughness of the second top surface. A method for manufacturing the semiconductor structure is also provided.