A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.

A diaphragm for a piezoelectric micromachined ultrasonic transducer (PMUT) is presented having resonance frequency and bandwidth characteristics which are decoupled from one another into independent variables. Portions of at least the piezoelectric material layer and backside electrode layer are removed in a selected pattern to form structures, such as ribs, in the diaphragm which retains stiffness while reducing overall mass. The patterned structure can be formed by additive, or subtractive, fabrication processes.

Various embodiments of the present disclosure are directed towards an integrated chip including a piezoelectric membrane overlying a substrate. A plurality of conductive layers is disposed within the piezoelectric membrane. The plurality of conductive layers comprises a first conductive layer over a second conductive layer. The first conductive layer comprises a first electrode and the second conductive layer comprises a second electrode. A first conductive via is disposed in the piezoelectric membrane and contacts the first electrode. A second conductive via is disposed in the piezoelectric membrane and contacts the second electrode. A sidewall of the second conductive via comprises a vertical sidewall segment overlying a slanted sidewall segment.

A method of manufacturing a vibration element includes: a first protective film forming step of forming a first protective film on a first substrate surface of a crystal substrate; a first dry etching step of dry-etching the crystal substrate via the first protective film; a second protective film forming step of forming a second protective film on a second substrate surface of the crystal substrate; and a second dry etching step of dry-etching the crystal substrate via the second protective film. A relationship of T1<T2<T3 or T4<T5<T6 is satisfied, in which T1 and T4 are thicknesses of the first and second protective films in an inter-arm region, respectively, T2 and T5 are thicknesses of the first and second protective films in first and second groove forming regions, respectively, and T3 and T6 are thicknesses of the first and second protective films in first and second bank portion forming regions, respectively.

A method of manufacturing a vibration element includes: a first protective film forming step of forming a first protective film on a first substrate surface of a crystal substrate; a first dry etching step of dry-etching the crystal substrate via the first protective film; a second protective film forming step of forming a second protective film on a second substrate surface of the crystal substrate; and a second dry etching step of dry-etching the crystal substrate via the second protective film. A relationship of T1<T2<T3 or T4<T5<T6 is satisfied, in which T1 and T4 are thicknesses of the first and second protective films in an inter-arm region, respectively, T2 and T5 are thicknesses of the first and second protective films in first and second groove forming regions, respectively, and T3 and T6 are thicknesses of the first and second protective films in first and second bank portion forming regions, respectively.

A structure comprising a semiconductor substrate and a layer of PZT (lead zirconate titanate) is etched by performing a first plasma etch step with a first etch process gas mixture. The first etch process gas mixture comprises at least one fluorine containing species. The first plasma etch step is performed so that involatile metal etch products are deposited onto interior surfaces of the chamber. The structure is further etched by performing a second plasma etch step with a second etch process gas mixture. The second etch process gas mixture comprises at least one fluorocarbon species. The second plasma etch step is performed so that a fluorocarbon polymer layer is deposited onto interior surfaces of the chamber to overlay involatile metal etch products deposited in the first plasma etch step and to provide a substrate on which further involatile metal etch products can be deposited.

A layered portion includes, at least above an opening, a first single-crystal piezoelectric body layer, a second single-crystal piezoelectric body layer, an intermediate electrode layer, a lower electrode layer, and an upper electrode layer. The first single-crystal piezoelectric body layer includes a material that produces a difference in etching rate between a positive side and a negative side of a polarization charge. The polarization charge of the first single-crystal piezoelectric body layer is negative on a side of the intermediate electrode layer and positive on a side of the lower electrode layer.

A method for making a piezoelectric microelectromechanical systems (MEMS) microphone is provided, comprising depositing a piezoelectric film layer onto a substrate; selectively etching the piezoelectric film layer to define lines; removing the substrate to define a cavity; and breaking the piezoelectric film layer along the lines, such that the microphone has at least two cantilevered beams. The piezoelectric microelectromechanical systems (MEMS) microphone is also provided.

A piezoelectric device including a substrate, a metal-insulator-metal element, a hydrogen blocking layer, a passivation layer, a first contact terminal and a second contact terminal is provided. The metal-insulator-metal element is disposed on the substrate. The hydrogen blocking layer is disposed on the metal-insulator-metal element. The passivation layer covers the hydrogen blocking layer and the metal-insulator-metal element. The first contact terminal is electrically connected to the metal-insulator-metal element. The second contact terminal is electrically connected to the metal-insulator-metal element.

A layered portion includes, at least above an opening, a first single-crystal piezoelectric body layer, a second single-crystal piezoelectric body layer, an intermediate electrode layer, a lower electrode layer, and an upper electrode layer. The first single-crystal piezoelectric body layer includes a material that produces a difference in etching rate between a positive side and a negative side of a polarization charge. The polarization charge of the first single-crystal piezoelectric body layer is positive on a side of the intermediate electrode layer and negative on a side of the lower electrode layer