Nano-scale junctions, wires, and junction arrays are created by using a focused high-energy ion beam to direct-write insulating or poorly conducting barriers into thin films of materials that are sensitive to disorder, including superconductors, ferromagnetic materials and semiconductors.

An interconnect may have a first end coupled to a superconducting system and a second end coupled to a non-superconducting system. The interconnect may include a superconducting element having a critical temperature. During operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end may have a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end may have a second temperature above the critical temperature of the superconducting element, and the interconnect may further be configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

An interconnect may have a first end coupled to a superconducting system and a second end coupled to a non-superconducting system. The interconnect may include a superconducting element having a critical temperature. During operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end may have a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end may have a second temperature above the critical temperature of the superconducting element, and the interconnect may further be configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

A high temperature superconducting device including a substrate, a high temperature superconducting thin film disposed on the substrate and one or more non-superconducting thin film regions formed adjacent to and across a substantially entire thickness of the high temperature superconducting thin film. In the high temperature superconducting device, the one or more non-superconducting thin film regions are formed from degrading corresponding superconducting materials same to the high temperature superconducting thin film through applying an external voltage. In addition, the one or more non-superconducting thin film regions and the high temperature superconducting thin film form one or more Josephson tunnel junctions.

An electronics device comprises a substrate, a first layer of a first layered material arranged over the substrate, a second layer of a second layered material arranged over the substrate, an overlap region, and a contact layer. In the overlap region, the second layer is arranged over the first layer, and a section of a bottom surface of the second layer is parallel to a section of a top surface of the first layer. The contact layer comprises a plurality of electrically conductive lines and an electrical insulation element. The plurality of electrically conductive lines comprises a first electrically conductive line and a second electrically conductive line. The first electrically conductive line and/or the second electrically conductive line comprises a superconductor material.

A method for measuring conductance of a material real-time during etching/milling includes providing a fixture having a socket for receiving the material. The socket is attached to a printed circuit board (PCB) mounted on one side of a plate that has at least one opening for providing ion beam access to the material sample. Conductive probes extend from the other side of the PCB to contact and span a target area of the material. A measurement circuit in electrical communication with the probes measures the voltage produced when a current is applied across the material sample to measure changes in electrical properties of the sample over time.

Solid-state devices including a layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate, the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof, and one or more layers of a semiconducting or insulating or metallic material epitaxially grown on the layer of superconductor material, the semiconducting or insulating material being one of a Group III N material or alloys thereof or a Group 4b N material or SiC or ScN or alloys thereof.

A qubit device comprises first and second superconductor layers a capacitor, first and second interconnects. The first superconductor layer comprises a first c-axis perpendicular to covalently bound atomic layers. The second superconductor layer comprises a second c-axis perpendicular to covalently bound atomic layers. The first and second superconductor layers form a Josephson junction, wherein the first c-axis and the second c-axis are aligned with each other at the Josephson junction. The aligned first and second c-axes intersect both the first superconductor layer and the second superconductor layer. The capacitor comprises a first electrode and a second electrode. The first interconnect electrically connects the first electrode and the first superconductor layer. The second interconnect electrically connects the second electrode and the second superconductor layer. The capacitor is arranged at a vertical position exceeding the vertical positions of both the first superconductor layer and the second superconductor layer.

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy. By orienting the same crystal axis in each case perpendicularly to the step edge on both sides of the step edge, a maximal supercurrent can flow across the grain boundary induced by the step edge, and consequently across the Josephson junction.