In an embodiment, a device includes a substrate having a thickness, wherein the thickness is a function of energy dissipation of a particle. In an embodiment, the device includes a thermal layer, formed on the substrate, of a first material that exhibits at least a threshold level of thermal conductivity, wherein the threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates, and wherein any intervening material exhibits at least a second threshold level of thermal conductivity, wherein the threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates.

Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.

An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

A device includes a first substrate formed of a first material that exhibits a threshold level of thermal conductivity. The threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, the device also includes a second substrate disposed in a recess of the first substrate, the second substrate formed of a second material that exhibits a second threshold level of thermal conductivity. The second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, at least one qubit is disposed on the second substrate. In an embodiment, the device also includes a transmission line configured to carry a microwave signal between the first substrate and the second substrate.

Quantum computing devices include a chip carrier that has a conductive carrier body and one or more readout resonators in the conductive carrier body. Each readout resonator has a center conductor and a coaxial dielectric layer. A quantum chip is on the chip carrier and includes one or more qubits positioned over respective readout resonators.

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

Quantum computing assemblies with through-hole dies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a package substrate, a quantum processing die, and a through-hole die between the package substrate and the quantum processing die, wherein the quantum processing die is electrically coupled to the package substrate by interconnects extending through through-holes of the through-hole die.

Methods and apparatuses are provided for controlling the state of a qubit. A qubit apparatus includes a load, a qubit, and a compound Josephson junction coupler coupling the qubit to the load. A coupling controller controls the coupling strength of the compound Josephson junction coupler such that a coupling between the qubit and the load is a first value when a reset of the qubit is desired and a second value during operation of the qubit.

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.