The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.

An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

A method of laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on Bi.sub.2Se.sub.3/WS.sub.2 at room temperature, comprising the steps of applying a laser to the Bi.sub.2Se.sub.3/WS.sub.2, writing a submicron pixel, wherein the submicron pixel has a circular polarization, modifying the circular polarization, allowing the circular polarization to be tuned across a range of 39.9%, tuning photoluminescence intensity, and tuning photoluminescence peak position. A method of growing Bi.sub.2Se.sub.3/WS.sub.2 as a nano-material or two-dimensional heterostructure for laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on the Bi.sub.2Se.sub.3/WS.sub.2 heterostructure at room temperature.

Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.

A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.