Patent classifications
H10N70/026
RESISTIVE MEMORY DEVICES AND ARRAYS
A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.
Projected memory device with carbon-based projection component
A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.
PHASE CHANGE MEMORY HAVING A COMPOSITE MEMORY ELEMENT
A phase change memory device with a composite memory element includes first and second layers of memory materials, and the composite memory element has a basis phase change material, such as a chalcogenide, and one or more additives, where the first layer of memory material is formed using oxygen-free atmosphere and the second layer of memory material is formed using oxygen-containing atmosphere. The use of “oxygen-free” atmosphere can prevent oxidation at the electrode surface of the first electrode.
Physical vapor deposition methods and systems to form semiconductor films using counterbalance magnetic field generators
Embodiments relate generally to semiconductor device fabrication and processes, and more particularly, to systems and methods that implement magnetic field generators configured to generate rotating magnetic fields to facilitate physical vapor deposition (“PVD”). In one embodiment, a system generates a first portion of a magnetic field adjacent a first circumferential portion of a substrate, and can generate a second portion of the magnetic field adjacent to a second circumferential portion of the substrate. The second circumferential portion is disposed at an endpoint of a diameter that passes through an axis of rotation to another endpoint of the diameter at which the first circumferential portion resides. The second peak magnitude can be less than the first peak magnitude. The system rotates the first and second portions of the magnetic fields to decompose a target material to form a plasma adjacent the substrate. The system forms a film upon the substrate.
MEMORY SELECTOR
A selector for a memory cell, intended to change from a resistive state to a conductive state so as to respectively prohibit or authorize access to the memory cell, characterized in that it is made of an alloy consisting of germanium, selenium, arsenic and tellurium.
Switching element, variable resistance memory device, and method of manufacturing the switching element
A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.
Scaled nanotube electrode for low power multistage atomic switch
A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
Techniques for dopant implantation and multilayer oxides for resistive switching devices
The techniques described herein relate to methods and apparatus for a resistive switching device. The resistive switching device includes a first electrode formed in a substrate. The resistive switching device also includes a plurality of layers formed above the first electrode, including a plurality of oxide layers, wherein one or more of the plurality of oxide layers comprise doped oxide layers, and one or more conductive spacers, wherein each pair of oxide layers of the plurality of oxide layers are separated by a conductive spacer of the one or more conductive spacers. The resistive switching device also includes a second electrode formed above the plurality of layers, such that the first electrode, the plurality of layers, and the second electrode are in series.
NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.
SPUTTERING TARGET INCLUDING CARBON-DOPED GST AND METHOD FOR FABRICATING ELECTRONIC DEVICE USING THE SAME
A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).