Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 510.sup.8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.

A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.

A resistive switching memory cell comprising a switchable solid electrolyte (E). The electrolyte (E) consists of a composition comprising a matrix comprising a metal oxide, metal sulphide and/or metal selenide as the matrix material, the metal oxide, metal sulphide and/or metal selenide comprising at least two metals M1 and M2, and a metal M3 which is mobile in the matrix. The atomic ratio of M1 to M2 is within the range of 75:25 to 99.99:0.01, preferably 90:10 to 99.99:0.01; the valence states of M1, M2 and M3 are all positive; the valence state of M1 is larger than the valence state of M2; the valence state of M2 is equal to or larger than the valence state of M3; and the metals M1, M2 and M3 are different.

A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

Disclosed is a method of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, the mold layer having a hole exposing a portion of the substrate, forming a phase transition layer with a void, in the hole, and thermally treating the phase transition layer to remove the void from the phase transition layer. The thermal treating of the phase transition layer may include heating the substrate to a first temperature to form a diffusion layer in the phase transition layer, and the first temperature may be lower than or equal to 55% of a melting point of the phase transition layer.