A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.

A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.

A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.