A method of manufacturing an electronic device comprises: forming a plurality of line patterns on a substrate extending in a first direction and including a first conductive line and a memory pattern; forming a first liner layer on sidewalls of each of the plurality of line patterns, the first liner layer including a plurality of layers having different energy band gaps; forming an insulating interlayer on the substrate; forming a plurality of second conductive lines on the line patterns and the insulating interlayer; etching the first liner layer, the insulating interlayer and the memory pattern using the second conductive lines as an etch barrier to expose the first conductive line to form a plurality of memory cells; and forming a second liner layer on both sidewalls of each of the memory cells, the etched first liner layer and both sidewalls of the etched insulating interlayer.

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.

A resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure through the plurality of insulating layers and the plurality of conductive layers; a plurality of insulating patterns formed on a sidewall of each of the plurality of interlayer insulating layers within the hole; a channel layer formed along a sidewall of each of the plurality of conductive layers within the hole and a sidewall of each of the plurality of the insulating patterns within the hole, wherein the channel layer includes convex regions that are adjacent to the insulating patterns and are convexly formed in relation to a central portion of the hole and includes concave regions that are adjacent to the plurality of conductive layers and are concavely formed in relation to the central portion of the hole.

There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.

A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

The present invention discloses a method for manufacturing a phase change memory and a phase change memory. The method comprises: forming a first wafer having a semiconductor-on-insulator structure; forming a memory material layer on the semiconductor-on-insulator structure; and forming a first metal material layer on the memory material layer to form a first semiconductor element.

Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.