A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 μs to about 54 μs.

A semiconductor memory device has a first wiring extending in a first direction and a second wiring extending in a second direction. The first and second wirings are spaced from each other in a third direction. The second wiring has a first recess facing the first wiring. A resistance change memory element is connected between the first and second wirings. A conductive layer is between the resistance change memory element and the second wiring and includes a first protrusion facing the second wiring. A switching portion is between the conductive layer and the second wiring and includes a second recess facing the conductive layer and a second protrusion facing the second wiring. The first protrusion is in the second recess. The second protrusion is in the first recess. The switching portion is configured to switch conductivity state according to voltage between the first wiring and the second wiring.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

The disclosure belongs to the field of microelectronics, and specifically, relates to a method of inducing crystallization of a chalcogenide phase-change material and application thereof. To be specific, a dielectric material is brought into contact with an interface of the chalcogenide phase-change material. The dielectric material is in an octahedral configuration, and the dielectric material provides a crystal nucleus growth center for the crystallization of the chalcogenide phase-change material at the interface between the two, so as to induce the phase-change material to accelerate the crystallization. The method is further applied in a phase-change memory cell. Among all the dielectric material layers in contact with the chalcogenide phase-change material layer, the dielectric material structure of at least one side of the dielectric material layer is an octahedral configuration.

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.

A phase change memory and a method of fabricating the same are provided. The phase change memory includes a lower electrode, an annular heater disposed over the lower electrode, an annular phase change layer disposed over the annular heater, and an upper electrode. The annular phase change layer and the annular heater are misaligned in a normal direction of the lower electrode. The upper electrode is disposed over the annular phase change layer, in which the upper electrode is in contact with an upper surface of the annular phase change layer. The present disclosure simplifies the manufacturing process of the phase change memory, reduces the manufacturing cost, and improves the manufacturing yield. In addition, a contact surface between the heater and the phase change layer of the phase change memory of the present disclosure is very small, so that the phase change memory has an extremely low reset current.

A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

A method includes providing a substrate having a main surface, forming a layer of thermally insulating material on the main surface, forming strips of phase change material on the layer of thermally insulating material such that strips of phase change material are separated from the main surface by thermally insulating material, forming first and second RF terminals on the main surface that are laterally spaced apart from one another and connected to the strips of phase change material, and forming a heater structure having heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material, wherein each of the strips of phase change material includes multiple outer faces, and wherein portions of both outer faces from the strips of phase change material are disposed against one of the heating elements.

A method for manufacturing a high-density three-dimensional programmable memory, relating to the memory manufacturing technology, comprises the following steps: 1) forming a base structure; 2) grooving the base structure; 3) disposing, storage medium layers required by a preset memory structure layer by layer on an inner wall of the division groove; 4) filling a core medium in the division groove to form a core medium layer; 5) etching, through a mask etching process, to form deep holes along the separation division groove filled with the core where the deep holes truncate the core medium in the division groove; and 6) filling an insulation medium in the deep holes. The method has the beneficial effects of low costs and the highest storage density.