In a method of manufacturing a semiconductor integrated circuit device, a pillar may be formed on a semiconductor substrate. A hard mask pattern may be formed on a top surface and a portion of a sidewall of the pillar. An electric field-buffering region may be formed in the sidewall of the pillar. A gate insulating layer may be formed on an outer surface of the pillar. A gate may be formed on the gate insulating layer.

Resistive memory devices are provided which are configured to mitigate resistance drift. A device comprises a phase-change element, a resistive liner, a first electrode, a second electrode, and a third electrode. The resistive liner is disposed in contact with a first surface of the phase-change element. The first electrode is coupled to a first end portion of the resistive liner. The second electrode is coupled to a second end portion of the resistive liner. The third electrode is coupled to the first surface of the phase-change element.

A structure including a bottom electrode, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the substrate, a top electrode on and vertically aligned with the phase change material layer, a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer. A structure including a phase change material layer selected from amorphous silicon, amorphous germanium and amorphous silicon germanium, a top electrode on the phase change material layer, a bottom electrode, a dielectric material isolating the bottom electrode from the top electrode and the phase change material layer. Forming a bottom electrode, forming a phase change material layer adjacent to the bottom electrode, forming a top electrode above the phase change material, forming a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer.

According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.

A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.

A method for producing a device includes depositing a lower electrode metal and a film whose resistance changes. The film whose resistance changes and the lower electrode metal are etched to form a pillar-shaped phase-change layer and a lower electrode. A reset gate insulating film and a reset gate metal are deposited and etched to form reset gates.

Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.

According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the superlattice structure portion, and a second layer provided on the other main surface of the superlattice structure portion in the deposition direction, which has a larger energy gap than that of the superlattice structure portion.

Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.