Provided herein is a phase change material for use in a display device. Also provided is a display device comprising a phase change material; the use of a phase change material as an optical absorber in a display device; a method of fabricating a pixel; and a method of fabricating a display device. The phase change material is as described in more detail herein.

2D heterostructures comprising Bi.sub.2Se.sub.3/MoS.sub.2, Bi.sub.2Se.sub.3/MoSe.sub.2, Bi.sub.2Se.sub.3/WS.sub.2, Bi.sub.2Se.sub.3/MoSe.sub.2. .sub.2xS.sub.2x, or mixtures thereof in which oxygen is intercalated between the layers at selected positions provide high density storage devices, sensors, and display devices. The properties of the 2D heterostructures can be configured utilizing abeam of electromagnetic waves or particles in an oxygen controlled atmosphere.

A neuron circuit includes: an input terminal to which spike signals are continuously input; a first switch element that has a first end coupled to the input terminal and a second end coupled to a node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when spike signals are input within a time period; a feedback circuit coupled to the node, and causing the input terminal to be at a level when the first switch element goes into the low resistance state; and a second switch element that is connected in series with the first switch element between the input terminal and the node, remains in a low resistance state even when spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the level.

An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.

A memory device includes a conductive wire, a first 2-D material layer, a phase change element, and a top electrode. The first 2-D material layer is over the conductive wire. The phase change element extends along a surface of the first 2-D material layer distal to the conductive layer. The top electrode is over the phase change element.

Aspects of the present disclosure are directed to a reconfigurable interference device comprising a phase change structure. The phase change structure comprises a solid-state phase change material having a first phase state and a second phase state dependent on temperature. A first energy source is configured to supply an initialization energy to initialize a plurality of domains having the first phase state and a second energy source is configured to supply an electrical current to the structure to position the plurality of domains of the first phase state within the phase change structure. A control unit is configured to control the first and the second energy source and to create a periodic interference pattern comprising a plurality of domains of the first phase state and a plurality of domains of the second phase state in an alternating pattern.

Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.

A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level. Each of the one or more programmable horizontal bridges electrically connects two respective conductive lines of the plurality of conductive lines in the first wiring level. The one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive.

Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.