[Problem]: The problem of the present invention is to provide a stacked structure excellent in stability of atomic arrangement, a method of manufacturing same, and a semiconductor device using the stacked structure. [Solution]: The stacked structure of the present invention is characterized in that it has an alloy layer A having germanium and tellurium as a main component and an alloy layer B having tellurium and either of antimony or bismuth as a main component, and at least either of the alloy layer A or the alloy layer B contains at least either of sulfur or selenium as a chalcogen atom.

In a method for forming a semiconductor device, a plurality of conductive lines is formed as a part of a first wiring level of the semiconductor device. The first wiring level is positioned over a first level having a plurality of transistor devices. The plurality of conductive lines extends parallel to the first level. In addition, a programmable horizontal bridge is formed that extends parallel to the first level, and electrically connects a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level. The programmable horizontal bridge is formed based on a programmable material that changes phase between a conductive state and a non-conductive state according to a current pattern delivered to the programmable horizontal bridge.

A cross-point memory semiconductor structure and a method of creating the same are provided. There is a first electrode layer on top of the substrate. A conductive oxide diffusion barrier layer is on top of the first electrode. A polycrystalline silicon diode is on top of the conductive oxide diffusion barrier. A phase change material (PCM) layer is on top of the polycrystalline silicon diode. A second electrode is on top of the PCM layer.

A three dimensional (3D) memory array is disclosed. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell. Methods to operate and to form the 3D memory array are disclosed.

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.

An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.

An exemplary semiconductor incorporates phase change material Mo.sub.xW.sub.1-xTe.sub.2 that may be the semiconducting channel or may be part of a control terminal/gate of the semiconductor. The phase change material selectably being in one of metal and insulator phases depending on whether a voltage field greater than a predetermined phase change field is present at the phase change material. The properties of the semiconductor are varied depending on the phase of the phase change material.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.