A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.

A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

A memory circuit includes a plurality of memory cells, each memory cell including a resistive memory element and a selection transistor of the FDSOI type connected in series with the resistive memory element. The selection transistor includes a channel region, a buried insulating layer, a back gate separated from the channel region by the buried insulating layer. The memory circuit further includes a circuit for biasing the back gate of the selection transistors, the biasing circuit being configured to apply a forward back-bias to the selection transistor of at least one memory cell during a programming or initialisation operation of the at least one memory cell.

A three-dimensional array device with multiple layers in height direction includes a first two-dimensional array circuit located in a first layer; and a second two-dimensional array circuit located in a second layer adjacent to the first layer and overlapped in a plan view with the first two-dimensional array circuit. Each of the first two-dimensional array circuit and the second two-dimensional array circuit has a first wiring group, an input part that inputs signals to the first wiring group, a second wiring group that intersects the first wiring group and an output part that outputs signals from the second wiring group. The output part in the first two-dimensional array circuit is overlapped in a plan view on the input part in the second two-dimensional array circuit and is connected in a signal transferable manner.

A resistive memory device includes: conductive layers and interlayer insulating layers, which are alternatively stacked; a vertical hole vertically penetrating the conductive layers and the interlayer insulating layers; a gate insulating layer disposed over an inner wall of the vertical hole; a charge trap layer disposed over an inner wall of the gate insulating layer; a channel layer disposed over an inner wall of the charge trap layer; and a variable resistance layer disposed over an inner wall of the channel layer.

Provided is a memory device and an electronic device including the same. The memory device according to an example embodiment may include: a two-dimensional material layer including a two-dimensional material; a contact region in contact with an edge of the two-dimensional material layer; and an electrode which is electrically connected to the contact region and changes a domain of a region adjacent to the contact region of the two-dimensional material layer by an applied voltage.

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.