Patent classifications
H10N70/8413
PHASE-CHANGE MEMORY CELL, AND METHOD FOR MANUFACTURING THE PHASE-CHANGE MEMORY CELL
A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.
COMPOSITE MATERIAL PHASE CHANGE MEMORY CELL
A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.
Electronic chip with two phase change memories
An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
MULTI-LAYER PHASE CHANGE MEMORY DEVICE
A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.
SELECTIVE STOP TO CONTROL HEATER HEIGHT VARIATION
A method, phase change memory array, and system for controlling heater height variation in phase change memories using a multi-step selective stop method. The method may include depositing a first dielectric layer. The method may also include depositing a second dielectric layer proximately connected to the first dielectric layer, where the second dielectric layer is different than the first dielectric layer. The method may also include depositing a heating material. The method may also include performing a first selective stop to remove excess heating material above the second dielectric layer. The method may also include performing a second selective stop to remove the second dielectric layer.
SELECTIVE ENCAPSULATION OF MEMRISTIVE ELEMENT
A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.
PHASE-CHANGE MATERIAL-BASED XOR LOGIC GATES
An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.
MULTI-LEVEL PROGRAMMING OF PHASE CHANGE MEMORY DEVICE
A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.
Method of manufacturing a semiconductor integrated circuit device including a transistor with a vertical channel
In a method of manufacturing a semiconductor integrated circuit device, a pillar may be formed on a semiconductor substrate. A hard mask pattern may be formed on a top surface and a portion of a sidewall of the pillar. An electric field-buffering region may be formed in the sidewall of the pillar. A gate insulating layer may be formed on an outer surface of the pillar. A gate may be formed on the gate insulating layer.
Programming Current Control for Artificial Intelligence (AI) Devices
Techniques for controlling the programming current of a PCM-based AI device using an external resistor are provided. In one aspect, a PCM cell includes: a PCM stack, that has a bottom electrode; a heater disposed directly on the bottom electrode; a PCM unit including a first material disposed on the heater; a top electrode including a second material disposed on the PCM unit; and a resistor adjacent to the PCM stack, wherein the resistor includes a combination of the first material and the second material. A PCM device that includes at least one of the PCM cells, and a method of forming the PCM cell are also provided.