According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode over the bottom electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the top electrode and the switching layer. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

An resistive random-access memory (RRAM) device including an first crystalline semiconductor layer disposed adjacent to a crystalline semiconductor substrate, a crystal lattice edge-dislocation segment disposed at an interface of the first crystalline semiconductor layer and crystalline semiconductor substrate, the lattice edge-dislocation segment including first and second segment ends, a first ion-source electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the first segment end of the lattice edge-dislocation segment, and a second electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the second segment end of the lattice edge-dislocation segment.

Disclosed are electrochemically tunable metamaterials which are capable of complete reversibility such that the metamaterial itself can physically disappear (out of the active region) and reappear later, in a controllable manner. Some variations provide an electrochemically tunable, solid-state metamaterial-based device comprising a plurality of metamaterial unit cells, wherein each of the metamaterial unit cells comprises: an ion conductor containing mobile metal ions; a first electrode in contact with the ion conductor, wherein the first electrode is contained in a metasurface negative space disposed on the ion conductor; a second electrode in contact with the ion conductor, wherein the second electrode is electrically isolated from the first electrode; and a metal-containing region containing one or more metals, wherein the metal-containing region is contained within a metasurface positive space disposed on the ion conductor.

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

A memory structure is provided. The memory structure includes a top terminal, a multi-level nonvolatile electrochemical cell, a bottom terminal, a pedestal contact in the same metal level as the bottom terminal, and a vertical conductor fully self-aligned to the multi-level nonvolatile electrochemical cell and extending vertically from the pedestal contact.

A two-terminal atom-based switching device having a fast operating speed and high durability and a manufacturing method thereof are disclosed. It is possible to reduce a forming voltage during positive voltage forming by forming an oxygen vacancy percolation path through negative voltage forming, which is first forming, and forming high binding energy and low formation energy between oxygen vacancies and metal ions implanted through positive voltage forming which is second forming after the negative voltage forming. Further, since a significant amount of metal ions implanted into the insulating layer through negative voltage application switching after the positive voltage forming is removed, the volatility of the two-terminal atom-based switching device may be improved, and a stuck-on failure phenomenon in the durability may be prevented.

A memory cell and formation thereof. The memory cell including: a first dielectric material having a via; a dielectric spacer on a sidewall of the via, and a second dielectric material pinching off the via and forming a seam.