A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.

Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.

A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

A memory device and method of making the same is provided. The memory device comprises a first electrode having a length along a first axis, a second electrode having a length along a second axis that is perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is positioned between a first electrode edge and a second electrode portion. The cross-sections of the first and second electrodes may have a polygonal shape.

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.

Interface engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a first geometric confining layer formed on the bottom electrode. The first geometric confining layer comprises a first plurality of pin-holes. The apparatus further comprises a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and a top electrode formed on the base oxide layer. The base oxide layer comprises one of: TaO.sub.x, HfO.sub.x, TiO.sub.x, ZrO.sub.x, or a combination thereof; the first geometric confining layer comprises Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Y.sub.2O.sub.3, Gd.sub.2O.sub.3, Sm.sub.2O.sub.3, CeO.sub.2, Er.sub.2O.sub.3, or a combination thereof.

A microelectronic device and method for manufacturing a microelectronic device comprising a plurality of resistive memories, a part of these resistive memories, called PUF memories, forming a PUF, the rest of these resistive memories being known as storage memories. The manufacturing process comprising forming a dielectric layer having on at least one contact surface in contact with an electrode a surface roughness of said surface greater than that of the same dielectric layer of the storage memories.

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.