A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.

An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.

A confined phase-change memory cell with self-aligned electrode includes a first conductive structure within a first dielectric layer. A phase-change memory pillar including a first portion of a phase-change material is confined within a second dielectric layer and electrically connected to the first conductive structure. A second conductive structure within a third dielectric layer is surrounded by a second portion of the phase-change material for electrically connecting the second conductive structure to the phase-change memory pillar and reducing heat loss.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.