According to one embodiment, a memory device includes first and second electrically conductive portions, a first variable resistance portion, and a first region. A direction from the first electrically conductive portion toward the second electrically conductive portion is aligned with a first direction. The first variable resistance portion is provided between the first and second electrically conductive portions. A second direction from the first variable resistance portion toward the first region crosses the first direction. The first region includes a first layer portion, and a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction. A first distance between the first and second layer portions is longer than first or second lattice length. The first lattice length is a lattice length of the first layer portion. The second lattice length is a lattice length of the second layer portion.

A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.

Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.

Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.

A mushroom memory cell may be formed by depositing a second dielectric layer on top of a first dielectric layer and a heater, depositing a hard mask on top of the second dielectric layer, performing a directional reactive-ion etching to remove an exposed portion of the second dielectric layer, performing a lateral etching to remove a portion of the second dielectric layer under the hard mask, performing directional deposition of a phase change material (PCM) over the heater, depositing a covering dielectric over the PCM, performing a second directional etching to expose a top surface of the PCM, and depositing a top electrode on the surface of the PCM.

In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.

A radio frequency (RF) switch includes a heating element, an aluminum nitride layer situated over the heating element, and a phase-change material (PCM) situated over the aluminum nitride layer. An inside segment of the heating element underlies an active segment of the PCM, and an intermediate segment of the heating element is situated between a terminal segment of the heating element and the inside segment of the heating element. The aluminum nitride layer situated over the inside segment of the heating element provides thermal conductivity and electrical insulation between the heating element and the active segment of the PCM. The aluminum nitride layer extends into the intermediate segment of the heating element and provides chemical protection to the intermediate segment of the heating element, such that the intermediate segment of the heating element remains substantially unetched and with substantially same thickness as the inside segment.

Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

A phase change device includes a substrate with a top surface. A heater structure is disposed on the substrate. The heater structure has first and second sidewalls on opposite sides of the heater structure. A phase change element is disposed over the heater structure. The phase change element includes three connected portions. A first portion is disposed over the heater structure. A second portion is disposed over the first sidewall of the heater structure. A third portion is over a first portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.

A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.