A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD), forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.

According to one embodiment, a storage device includes a first conductive layer, a second conductive layer, a resistance-variable layer, between the first conductive layer and the second conductive layer, that includes germanium, antimony, and tellurium, a first layer, between the resistance-variable layer and the first conductive layer, that includes carbon, a second layer, between the resistance-variable layer and the second conductive layer, that includes carbon, a third layer, between the resistance-variable layer and the first layer, that includes at least one of tungsten nitride or tungsten carbide, and a fourth layer, between the resistance-variable layer and the second layer, that includes at least one of tungsten nitride or tungsten carbide.

A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD), forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.

A method of forming a memory structure includes forming an opening on opposing sides of a plurality of memory pillars disposed on a substrate, the opening extends through a capping layer located above a first dielectric layer and a top portion of an oxide layer, the oxide layer is located between the first dielectric layer and an encapsulation layer on the substrate, the encapsulation layer surrounds the plurality of pillars, removing the oxide layer from areas of the memory structure located between the memory pillars, above the encapsulation layer and below the first dielectric layer, after removing the oxide layer a gap remains within the areas of the memory structure, and forming a second dielectric directly above the capping layer, wherein the second dielectric layer pinches off the opening to form airgaps.

A radio frequency (RF) switch includes a heating element, an aluminum nitride layer situated over the heating element, and a phase-change material (PCM) situated over the aluminum nitride layer. An inside segment of the heating element underlies an active segment of the PCM, and an intermediate segment of the heating element is situated between a terminal segment of the heating element and the inside segment of the heating element. The aluminum nitride layer situated over the inside segment of the heating element provides thermal conductivity and electrical insulation between the heating element and the active segment of the PCM. The aluminum, nitride layer extends into the intermediate segment of the heating element and provides chemical protection to the intermediate segment of the heating element, such that the intermediate segment of the heating element remains substantially unetched and with substantially same thickness as the inside segment.

A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

The technology of a crossbar array circuit and method of improving thermal shielding are disclosed. An example apparatus includes a bottom wire; a first vertical thermal shielding layer formed on the bottom wire, a bottom electrode formed on the first vertical thermal shielding layer; a filament forming layer formed on the bottom electrode; a top electrode formed on the filament forming layer; a second vertical thermal shielding layer formed on the top electrode; a top wire formed on the second vertical thermal shielding layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the first vertical thermal shielding layer and the second vertical thermal shielding layer includes ReO.sub.x, RuO.sub.x, IrO.sub.x, ITO, a combination thereof, or an alloy or doping thereof (with or without other thermally conductive materials).

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.