A physical unclonable function device includes alternating regions of programable material and electrically conductive regions. The regions of programable material are configured to switch resistance upon receiving an electric pulse. An electric pulse applied between two outer electrically conductive regions of the alternating regions will switch the resistance of at least one region of programmable material. The alternating regions may include a plurality of the electrically conducting regions and a region of the programable material disposed between each of the plurality of electrically conductive regions. The resistance of each of the regions of programable material is selectively variable in at least a portion thereof as a result of the electric pulse flowing therethrough. The resistance value of the programable material region may be a readable value as a state of the device. The regions of programmable material may be formed of a phase change material or an oxide.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells. To reduce electrical discharge associated with current spikes, a first resistive film is formed in the access line between the left portion and the conductive layer, and a second resistive film is formed in the access line between the right portion and the conductive layer.

Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

Two-terminal resistive switching devices can have a switching layer in which a filament forms and deforms to varying degrees to represent distinct logical states. This switching layer can be formed having a varying ratio, X, of nitrogen to silicon at various strata of the switching layer. Such can result in a two-terminal memory device with improved stability and other characteristics. The switching layer can be formed in a vacuum chamber in which the gas mixture has a ratio, Y, of nitrogen gas to argon gas that is varied during fabrication

A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

A memory device is provided with a support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between a first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resist memory cells are arranged.

A memory device including a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell of the plurality of memory cells comprises a conductive ferroelectric material and wherein the conductive ferroelectric material is in series with a dielectric material.

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.