Provided are a substrate treating apparatus and method of manufacturing a phase-change layer having superior deposition characteristics. The substrate treating method of manufacturing a phase-change memory includes forming a bottom electrode on a substrate on which a pattern is formed, performing surface treating for removing impurities generated or remaining on a surface of the substrate while the bottom electrode is formed, performing nitriding on the surface of the substrate from which the impurities are removed, and successively depositing a phase-change layer and a top electrode on the bottom electrode. The substrate treating apparatus for manufacturing a phase-change memory includes a load lock chamber into/from which a plurality of substrates are loaded or unloaded, the load lock chamber being converted between an atmosphere state and a vacuum state, a nitriding chamber in which nitriding is performed on a surface of a substrate on which a bottom electrode is disposed, the nitriding chamber being coupled to one side of a plurality of sides of the vacuum transfer chamber, and a process chamber in which a phase-change layer is deposited on the surface of the substrate on which nitriding is performed in the nitriding process chamber, the process chamber being coupled to one of the plurality of sides of the vacuum transfer chamber.

A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

A memristor structure may be provided that includes a first electrode, a second electrode, and a buffer layer disposed on the first electrode. The memristor structure may include a switching layer interposed between the second electrode and the buffer layer to form, when a voltage is applied, a filament or path that extends from the second electrode to the buffer layer and to form a Schottky-like contact or a heterojunction between the filament and the buffer layer.

A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.

An electronic synaptic device includes: a lower electrode; an upper electrode; and an active layer provided between the lower electrode and the upper electrode and including a plurality of conductive nanoparticles, wherein the conductive nanoparticles are dispersed in a matrix forming a continuous phase, and the matrix is composed of a protein. The electronic synaptic device has a low switching operation voltage, is capable of implementing a transition phenomenon from a short term potentiation state to a long term potentiation state even with a relatively low voltage, and has high stability; and, therefore, can be preferably applied as a memristive device for implementing neuromorphic computing.

Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm.Math.cm.

A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.