A memory device comprising a memory array comprising a plurality of memory cells and a metal silicide layer, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupling a storage element to the first access line, wherein the metal silicide layer is between the electrode and the first access line.

Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

A method of manufacturing an OTS device of the invention is a method of manufacturing OTS device including a first conductor, an OTS portion made of chalcogenide, and a second conductor which are layered in order and disposed on an insulating substrate. The manufacturing method includes: a step D of forming a resist so as to coat part of an upper surface of the second conductor; a step E of dry etching a region which is not coated with the resist; and a step F of ashing the resist. In the step E, the second conductor, all of the OTS portion, and an upper portion of the first conductor are removed by an etching treatment once in a depth direction of the region.

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

Proposed are a layered Group III-V compound having ferroelectric properties, a Group III-V compound nanosheet that may be prepared using the same, and an electrical device including the materials. Proposed is a layered compound represented by [Formula 1] M.sub.x−mA.sub.yB.sub.z (M is at least one of Group I or Group II elements, A is at least one of Group III elements, B is at least one of Group V elements, x, y, and z are positive numbers which are determined according to stoichiometric ratios to ensure charge balance when m is 0, and 0<m<x), and having ferroelectric-like properties.

A confined phase-change memory cell with self-aligned electrode includes a first conductive structure within a first dielectric layer. A phase-change memory pillar including a first portion of a phase-change material is confined within a second dielectric layer and electrically connected to the first conductive structure. A second conductive structure within a third dielectric layer is surrounded by a second portion of the phase-change material for electrically connecting the second conductive structure to the phase-change memory pillar and reducing heat loss.

A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

A switching device having a first electrode, a second electrode, and a switching layer between the first and second electrodes, formed using a chalcogenide composition doped with an element that suppresses oxidation, which results in improved manufacturability and yield. For selector material based on AsSeGeSi or other chalcogenide materials that include selenium or arsenic, or other chalcogenide materials that include selenium or arsenic and silicon, the element added to suppress oxidation can be sulfur.