A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

A perpendicular bottom-free-layer STT-MRAM cell includes a bottom-free-layer magnetic tunnel junction (BMTJ). The BMTJ includes a composite metal oxide seed layer, and a free layer comprising boron (B) on the composite metal oxide seed layer. The composite metal oxide seed layer includes a first metal layer; a metal oxide layer on the first metal layer; and a second metal layer on the metal oxide layer. The second metal layer has been oxygen treated.

Systems and methods for reducing write error rate in MeRAM applications in accordance with various embodiments of the invention are illustrated. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a given period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect, and lowering the applied voltage of the given polarity before the end of the given period of time, wherein the given period of time is approximately half of a precessional period of the ferromagnetic free layer.

Various devices are described (along with methods for making them), where the device has a tunnel barrier sandwiched between two magnetic layers (one of the magnetic layers functioning as a free layer and the other of the magnetic layers functioning as a reference layer). One magnetic layer underlies the tunnel barrier and the other magnetic layer overlies the tunnel barrier, thereby permitting spin-polarized current to pass across the magnetic layers and through the tunnel barrier. At least one of the magnetic layers includes a metal oxide sublayer (e.g., an MgO sublayer) sandwiched between magnetic material.

Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction that has a free layer, a pinned layer and a tunnel barrier between the free layer and the pinned layer. The free layer has a switchable direction of magnetization perpendicular to the plane of the free layer. A cap layer is provided adjacent to the magnetic tunnel junction. The thickness of the cap layer is increased so that the cap layer acts as a heating layer, which results in a reduction of the current density during writing and increases the write margin. In some embodiments, a resistive heating layer is added to the memory cell, adjacent to the cap layer, in order to achieve the lower current density and increased write margin while also improving signal to noise ration during reading by eliminating shot noise.

Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.

Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.