A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400 C. or more.

Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

A stress sensor includes a stress detection layer including a laminated body including a first magnetic layer, a first non-magnetic layer, and a second magnetic layer that are laminated, wherein the first magnetic layer and the second magnetic layer have mutually different magnetoelastic coupling constants, such that a stress is detected by an electrical resistance dependent on a relative angle of magnetization between the first magnetic layer and the second magnetic layer varying depending on the stress externally applied.

A method of cleaning a substrate processing apparatus that etches a film including a metal includes (a) providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and (b) after (a), providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.

A magnetoresistive device includes first and second ferromagnetic regions and an intermediate region formed of a dielectric material between the first and second ferromagnetic regions. A surface of the intermediate region at an interface between the intermediate region and at least one of the first and second ferromagnetic regions may be a plasma treated surface.

A magnetoresistive element comprises a nonmagnetic nano-current-channel (NCC) structure provided on a surface of the magnetic recording layer, which is opposite to a surface of the magnetic recording layer where the tunnel barrier layer is provided, and comprising a spatial distribution of perpendicular conducting channels throughout the NCC structure thickness and surrounded by an insulating medium, making the magnetic recording layer a magnetically soft-hard composite structure. Correspondingly, the critical write current and write power are reduced with reversal modes of exchange-spring magnets of the magnetically soft-hard composite structure.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

A TMR element includes a base layer that is disposed on an upper surface of a via interconnect part, a magnetic tunnel junction that is disposed on a surface of the base layer, and an interlayer insulation layer that covers a side surface of each of the via interconnect part and the base layer. The base layer includes a stress relieving region. The magnetic tunnel junction includes a reference layer having a magnetization fixed direction, a magnetization free layer, and a tunnel barrier layer disposed between the reference layer and the magnetization free layer. The interlayer insulation layer includes an insulation material.