H01F10/3259

Textured cobalt aluminum/magnesium-aluminum-oxide pedestal for memory devices

A memory device including a pedestal structure containing a cobalt aluminum layer and a magnesium-aluminum-oxide containing base layer both of which have a (001) crystal orientation is provided. The memory device further includes a magnetic tunnel junction (MTJ) pillar containing an ordered alloy forming an interface with the cobalt aluminum alloy layer. The use of the structural and textural engineered pedestal structure provides improved control of resistance, as well as improved magnetic properties such as higher tunnel magnetoresistance (TMR) and higher perpendicular magnetic anisotropy (PMA), and closer distribution of the ordered alloy.

CRYSTAL SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM)
20250342874 · 2025-11-06 ·

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

Magnetoresistive stack and methods therefor

A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.

MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICES AND METHODS OF FORMING THE SAME
20250351738 · 2025-11-13 ·

Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.

Magneto-resistive random-access memory (MRAM) devices and methods of forming the same

Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.

Nitride diffusion barrier structure for spintronic applications

A magnetic tunnel junction (MTJ) is disclosed wherein a nitride diffusion barrier (NDB) has a L2/L1/NL or NL/L1/L2 configuration wherein NL is a metal nitride or metal oxynitride layer, L2 blocks oxygen diffusion from an adjoining Hk enhancing layer, and L1 prevents nitrogen diffusion from NL to the free layer (FL) thereby enhancing magnetoresistive ratio and FL thermal stability, and minimizing resistance x area product for the MTJ. NL is the uppermost layer in a bottom spin valve configuration, or is formed on a seed layer in a top spin valve configuration such that L2 and L1 are always between NL and the FL or pinned layer, respectively. In other embodiments, one or both of L1 and L2 are partially oxidized. Moreover, either L2 or L1 may be omitted when the other of L1 and L2 is partially oxidized. A spacer between the FL and L2 is optional.

Techniques for MRAM MTJ top electrode connection

Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.

Superparamagnetic tunnel junction element and computing system

A superparamagnetic tunnel junction element and a computing system using same, wherein the tunnel junction element has excellent operational stability against an external magnetic field and is suitable for the computing system based on probabilistic computing. The superparamagnetic tunnel junction element includes a first ferromagnetic layer group containing a ferromagnetic material, a second ferromagnetic layer group containing a ferromagnetic material, and a barrier layer disposed between the first ferromagnetic layer group and the second ferromagnetic layer group, wherein the first ferromagnetic layer group 14 includes a (1-1)th ferromagnetic layer, a (1-2)th ferromagnetic layer, and a first nonmagnetic coupling layer, the (1-1)th ferromagnetic layer is made of a ferromagnetic material, the magnetization direction thereof changes with a first time constant, the first time constant is one second or shorter, and the first nonmagnetic coupling layer contains at least one of Ru, Ir, Rh, Cr, and Cu.

TECHNIQUES FOR MRAM MTJ TOP ELECTRODE CONNECTION

Some embodiments relate to an integrated chip having a memory cell over a substrate. The memory cell includes a first electrode. An electrode contact is on an upper surface of the first electrode. A width of an upper surface of the electrode contact is greater than a width of the upper surface of the first electrode and a thickness of the electrode contact. A first conductive interconnect structure contacts the upper surface of the electrode contact. A width of the first conductive interconnect structure is greater than the width of the upper surface of the electrode contact. A second conductive interconnect structure overlies the first conductive interconnect structure. Thicknesses of the first and second conductive interconnect structures are greater than the thickness of the electrode contact.