H01F10/3259

COMPOSITIONS OF CHIRAL MOLECULES AND PEROVSKITE NANOCRYSTALS AND METHODS OF MAKING THE SAME

The present disclosure relates to a composition that includes a nanocrystalline core that includes a perovskite and having an outer surface, and a chiral molecule having a functional group, where the functional group is bonded to a first portion of the outer surface, and the composition is capable of circularly polarized luminescence (CPL). In some embodiments of the present disclosure, the composition is capable of absorbing circularly-polarized light.

Magnetic sensor bias point adjustment method

The present disclosure generally relates to a Wheatstone bridge that has four resistors. Each resistor includes a plurality of TMR structures. Two resistors have identical TMR structures. The remaining two resistors also have identical TMR structures, though the TMR structures are different from the other two resistors. Additionally, the two resistors that have identical TMR structures have a different amount of TMR structures as compared to the remaining two resistors that have identical TMR structures. Therefore, the working bias field for the Wheatstone bridge is non-zero.

MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODS
20210343933 · 2021-11-04 ·

The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

Magnetic tunnel junction structures and related methods

The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

SPIN TORQUE OSCILLATOR (STO) SENSORS USED IN NUCLEIC ACID SEQUENCING ARRAYS AND DETECTION SCHEMES FOR NUCLEIC ACID SEQUENCING

Disclosed herein are methods and apparatuses for sequencing nucleic acids using a detection device, the detection device comprising a plurality of spin torque oscillators (STOs) and at least one fluidic channel. In some embodiments of a method, a nucleotide precursor is labeled with a magnetic nanoparticle (MNP), and the labeled nucleotide precursor is added to the fluidic channel of the detection device. It is determined whether at least one of the plurality of STOs is generating a signal. Based at least in part on the determination of whether the at least one of the plurality of STOs is generating the signal, it is determined whether the labeled nucleotide precursor has been detected.

Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic laver

A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.

Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer

A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.

Magnetic random access memory and manufacturing method thereof

A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

Magnonic electromagnetic radiation sources with high output power at high frequencies

Acoustically mediated pulsed radiation sources, phased arrays incorporating the radiation sources, and methods of using the radiation sources and phased arrays to generate electromagnetic radiation via magnetic dipole emission are provided. The radiation sources are based on a superlattice heterostructure that supports in-phase magnetic dipole emission from a series of magnetic insulator layers disposed along the length of the heterostructure.

Memory device and semiconductor die, and method of fabricating memory device

A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.