Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.

A thin film inductor includes a body including a coil part disposed therein, wherein the coil part includes a patterned insulating film disposed on a substrate and a coil pattern formed between the patterned insulating films, the coil pattern having a lower height than the insulating film, such that the coil pattern may be formed in a structure with a high aspect ratio while having a uniform thickness, thereby increasing a cross-sectional area of the coil part and improving direct current resistance (Rdc) characteristics.

A method for manufacturing a multilayer coil includes preparing a first substrate by forming a first conductor pattern on a first insulating base material layer, preparing a second substrate by forming a second conductor pattern on a second insulating base material layer, and joining a surface of the first substrate on which the first conductor pattern is formed and a surface of the second substrate on which the second conductor pattern is formed together with only a joining layer made of a thermoplastic resin interposed therebetween. Amounts of deformation of the first and second insulating base material layers are less than that of the joining layer at a fusion temperature. The first and second conductor patterns are each a coil pattern having a coil axis that extends in a lamination direction in which the first substrate and the second substrate are laminated together.

A coil-incorporated multilayer substrate includes base materials and a coil portion including conductor patterns that are wound a plurality of times on at least one of the base materials, and, in a predetermined direction along the surface of the base material of the coil portion, the width of outermost conductor patterns is larger than the widths of the conductor patterns between an innermost conductor pattern and an outermost conductor pattern, the width of the innermost conductor pattern is larger than the widths of the conductor patterns between the outermost conductor pattern and the innermost conductor pattern, and the width of the innermost conductor pattern is larger than the distance between the innermost conductor pattern and the conductor pattern adjacent to the innermost conductor pattern.

A magnetic assembly includes a multilevel lamination or metallization structure with a core dielectric layer, dielectric stack layers, a high permittivity dielectric layer, and first and second patterned conductive features, the dielectric stack layers having a first relative permittivity, the high permittivity dielectric layer extends between and contacting the first patterned conductive feature and one of the dielectric stack layers or the core dielectric layer, the high permittivity dielectric layer has a second relative permittivity, and the second relative permittivity is at least 1.5 times the first relative permittivity to mitigate dielectric breakdown in isolation products.

A coil electronic component includes: a body including a substrate and coil parts disposed on first and second surfaces of the substrate; and external electrodes formed on outer surfaces of the body and connected to the coil parts. A metal layer is disposed within the substrate.

A process to form devices may include forming a seed layer on and/or over a substrate, modifying a seed layer selectively, forming an image-wise mold layer on and/or over a substrate and/or electrodepositing a first material on and/or over an exposed conductive area. A process may include selectively applying a temporary patterned passivation layer on a conductive substrate, selectively forming an image-wise mold layer on and/or over a substrate, forming a first material on and/or over at least one of the exposed conductive areas and/or removing a temporary patterned passivation layer. A process may include forming a sacrificial image-wise mold layer on a substrate layer, selectively placing one or more first materials in one or more exposed portions of a substrate layer, forming one or more second materials on and/or over a substrate layer and/or removing a portion of a sacrificial image-wise mold layer.

Provided is an electrically insulated component for use in a planar transformer. The insulated component may include a planar transformer conductive component having a first surface, a second surface and a plurality of edges. The insulated component may also include a first layer including an oxidized metal coating, as well as a second layer including an electrophoretically deposited (EPD) insulating coating. The EDP coating may include a polymer and an inorganic material. The first layer and the second layer may cover at least the first surface and the plurality of edges of the conductive component and the first layer may be disposed between the conductive component and the second layer. Also provided is a method of manufacturing of the electrically insulated component.

A device includes a dielectric layer having a first surface and a second surface. The device also includes a first set of high-aspect ratio electroplated structures disposed on the first surface of the dielectric layer and a second set of high-aspect ratio electroplated structures disposed on the second surface of the dielectric layer opposite the first set of high-aspect ratio electroplated structures.

In accordance with an embodiment, a circuit element includes a flexible foldable substrate having portions of a first inductor formed on first and second major surfaces of the flexible substrate. In accordance with another embodiment, a first electrically conductive trace having a first terminal, a second terminal, and a first annular-shaped portion between the first terminal and the second terminal is formed on a first portion of the first major surface. A second electrically conductive trace having a first terminal, a second terminal, a first annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace, and a second annular-shaped portion between the first terminal and the second terminal of the second electrically conductive trace is formed on the second major surface. The first electrically conductive trace is coupled to the second electrically conductive trace by a thru-via.