A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.

A method for manufacturing a magnetic memory element structure using a Ru hard mask and a self-aligned pillar formation process. A plurality of magnetic memory element layers are deposited over a substrate, including a magnetic reference layer, a non-magnetic barrier layer deposited over the magnetic reference layer, a magnetic free layer deposited over the non-magnetic barrier layer and a Ru hard mask layer deposited over the Ru hard mask layer. A mask structure is formed over the Ru hard mask and the image of the mask structure is transferred to the Ru hard mask. A first ion milling is performed to transfer the image of the patterned Ru hard mask onto the underlying magnetic free layer and non-magnetic barrier layer, the first ion milling being terminated when the magnetic reference layer has been reached. A non-magnetic dielectric protective layer is then deposited and a second ion milling is performed.

An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.

A multi-state memory and a method for manufacturing the same. A magnetoresistive tunnel junction is disposed on a spin-orbit coupling layer, and thermal annealing is performed after dopant ions are injected from a side of the magnetoresistive tunnel junction. The concentration of dopant ions in the magnetoresistive tunnel junction has a gradient variation along the direction that is perpendicular to the direction of the current and within the plane in which the spin-orbit coupling layer is located. Symmetry along the direction perpendicular to the direction of the current is broken. In a case a current flows into the spin-orbit coupling layer, resistance are outputted in multiple states in linearity with the current. The multi-state storage is achieved. It can meet a requirement on hardware of neural network synapses, and is applicable to calculation in a neural network.

In a method of etching according to one embodiment, a multilayer film having a magnetic tunnel junction layer is etched. In the method of etching, a plasma processing apparatus is used. A chamber body of the plasma processing apparatus provides an internal space. In the method of etching, a workpiece is accommodated in the internal space. Next, the multilayer film is etched by plasma of a first gas generated in the internal space. The first gas includes carbon and a rare gas and does not include hydrogen. Next, the multilayer film is further etched by plasma of a second gas generated in the internal space. The second gas includes oxygen and a rare gas and does not include carbon and hydrogen.

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

A method for producing a tunnel magnetoresistive element includes a stacking step, then in-magnetic field heating, and then dry etching. The stacking includes stacking a B absorption layer which is in contact with an upper surface of a CoFeB layer. The dry etching includes removal of layers to the B absorption layer. An end of etching is set as an end point time detected by an analysis device when a final layer before the B absorption layer directly above the CoFeB layer is exposed has reduced to a prescribed level, or when the B absorption layer directly above the CoFeB layer has increased to the prescribed level. An amount of over-etching after the end point time is specified in advance, and the B absorption layer is stacked such that the thickness from the prescribed level to the upper surface of the CoFeB layer corresponds to the over-etching amount.

A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.