An electronic assembly, has at least one circuit board with conductor tracks, at least one current-limiting arrangement in the form of a thermal predetermined breaking point in at least one of the conductor tracks, and a fire-containment device in the region of the current-limiting arrangement.

A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

A method comprises: forming a first metallization layer on a semiconductor die, the first metallization layer including a metal fuse; and forming a second metallization layer on the first metallization layer, in which the second metallization layer includes a thermal conductor spaced from the metal fuse, and the first metallization layer is between the second metallization layer and the semiconductor die.

A polymer positive temperature coefficient (PPTC) material is provided. The PPTC material may include a polymer matrix that defines a PPTC body, and further includes a high temperature polymer. The PPTC material may include a conductive filler component, disposed in the polymer matrix, an arc suppressant, and a high temperature antioxidant, disposed in the polymer matrix.

A polymer positive temperature coefficient (PPTC) material is provided. The PPTC material may include a polymer matrix that defines a PPTC body, and further includes a high temperature polymer. The PPTC material may include a conductive filler component, disposed in the polymer matrix, an arc suppressant, and a high temperature antioxidant, disposed in the polymer matrix.

A thermal fuse resistor including a ceramic substrate, a resistor body, a temperature sensing body, a first electrode cap, a second electrode cap, a first lead wire, a second lead wire, and a third lead wire. A first end of the ceramic substrate is provided with a first electrode cap, and a second end of the ceramic substrate is provided with a second electrode cap. The first electrode cap includes a main body, an inner end, and an outer end with an opening. The outer end includes an everted edge closely contacting the first end of the ceramic substrate. The main body and the inner end are arranged inside the ceramic substrate. The first lead wire extends outward from an outer end. One end of the third lead wire is electrically connected to the second electrode cap.

A varistor component and a method for securing a varistor component are disclosed. In an embodiment, a varistor includes a first external contact, a second external contact, a varistor electrically connected to the first external contact, a path between the varistor and the second external contact and an active releasing device including a shutter and a heat sensitive element, wherein the heat sensitive element releases the shutter under abnormal operation conditions and the shutter closes the path between the varistor and the second external contact.

A varistor component and a method for securing a varistor component are disclosed. In an embodiment, a varistor includes a first external contact, a second external contact, a varistor electrically connected to the first external contact, a path between the varistor and the second external contact and an active releasing device including a shutter and a heat sensitive element, wherein the heat sensitive element releases the shutter under abnormal operation conditions and the shutter closes the path between the varistor and the second external contact.

The disclosure provides an anti-short-circuit integrated chip and terminal facility. The integrated chip comprises: a control unit having a first output terminal configured for outputting a first signal and a second output terminal configured for outputting a second signal; and an insurance apparatus having a first insurance part connected to the first output terminal and a second insurance part connected to the second output terminal. The insurance parts are configured for limiting the currents flowed through the insurance parts when the currents flowed through the insurance parts exceed the current threshold. The chip device can be protected from being damaged when there is short circuit.

The disclosure provides an anti-short-circuit integrated chip and terminal facility. The integrated chip comprises: a control unit having a first output terminal configured for outputting a first signal and a second output terminal configured for outputting a second signal; and an insurance apparatus having a first insurance part connected to the first output terminal and a second insurance part connected to the second output terminal. The insurance parts are configured for limiting the currents flowed through the insurance parts when the currents flowed through the insurance parts exceed the current threshold. The chip device can be protected from being damaged when there is short circuit.