A field emission transistor uses carbon nanotubes positioned to extend along a substrate plane rather than perpendicularly thereto. The carbon nanotubes may be pre-manufactured and applied to the substrate and then may be etched to create a gap between the carbon nanotubes and an anode through which electrons may flow by field emission. A planar gate may be positioned beneath the gap to provide a triode structure.

Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer.

A vacuum micro-electronics device that utilizes fissile material capable of using the existing neutron leakage from the fuel assemblies of a nuclear reactor to produce thermal energy to power the heater/cathode element of the vacuum micro-electronics device and a self-powered detector emitter to produce the voltage/current necessary to power the anode/plate terminal of the vacuum micro-electronics device.

A method for manufacturing a microelectronic semiconductor device comprising the steps of: forming a trench in a body, the trench having side walls, a opening, and a bottom; forming a sacrificial layer in the trench; forming a recess in the sacrificial layer; forming a restriction structure between the sacrificial layer and the opening of the trench, defining a through hole for access to the sacrificial layer; completely removing the sacrificial layer through said through hole; and depositing a metal layer over the body, thus closing the opening of the trench and forming an electron-emission cathode tip.

In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer.

Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.