According to one aspect of the present invention, an electron beam apparatus includes charge amount distribution operation processing circuitry that operates a charge amount distribution of an irradiation region in a case that a substrate is irradiated with an electron beam using a combined function combining a first exponential function having an inflection point and at least one of a first-order proportional function and a second exponential function that converges and depending on a pattern area density; positional displacement operation processing circuitry that operates a positional displacement of an irradiation pattern formed due to irradiation of the electron beam using the charge amount distribution obtained; correction processing circuitry that corrects an irradiation position using the positional displacement; and an electron beam column including an emission source that emits the electron beam and a deflector that deflects the electron beam to irradiate a corrected irradiation position with the electron beam.

The invention relates to a collimator electrode stack (70), comprising: at least three collimator electrodes (71-80) for collimating a charged particle beam along an optical axis (A), wherein each collimator electrode comprises an electrode body with an electrode aperture for allowing passage to the charged particle beam, wherein the electrode bodies are spaced along an axial direction (Z) which is substantially parallel with the optical axis, and wherein the electrode apertures are coaxially aligned along the optical axis; and a plurality of spacing structures (89) provided between each pair of adjacent collimator electrodes and made of an electrically insulating material, for positioning the collimator electrodes at predetermined distances along the axial direction. Each of the collimator electrodes (71-80) is electrically connected to a separate voltage output (151-160). The invention further relates to a method of operating a charged particle beam generator.

A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles.

In order to solve the problem that information indicating three or more points on a contour of a figure drawn by an electron beam writer cannot be more precisely acquired, an information processing apparatus includes: an accepting unit that accepts pattern information indicating a pattern figure, and actually observed contour information acquired using an image obtained by capturing an image of a figure drawn by an electron beam writer; a transforming information acquiring unit that acquires transforming information, which is information that minimizes the sum of squares of differences between convolution values corresponding to three or more corrected contour points of a given point spread function in a region indicated by the pattern figure indicated by the pattern information and a threshold regarding the convolution values; a corrected contour point acquiring unit that acquires corrected contour point information, which is information indicating three or more corrected contour points respectively corresponding to three or more actually observed contour points, using the transforming information; and an output unit that outputs the corrected contour point information. Accordingly, it is possible to more precisely acquire information indicating three or more points on a contour of a figure drawn by an electron beam writer.

A method for exposing a wafer using a plurality of charged particle beamlets. The method comprises identifying non-functional beamlets among the beamlets, allocating a first subset of the beamlets for exposing a first portion of the wafer, the first subset excluding the identified non-functional beamlets, performing a first scan for exposing the first portion of the wafer using the first subset of the beamlets, allocating a second subset of the beamlets for exposing a second portion of the wafer, the second subset also excluding the identified non-functional beamlets, and performing a second scan for exposing the second portion of the wafer using the second subset of the beamlets, wherein the first and second portions of the wafer do not overlap and together comprise the complete area of the wafer to be exposed.

Systems and method directed to digital pattern generator (DPG) having a mirror array in an e-beam lithography system are discussed. The mirror array includes a first bank of mirrors and a second bank of mirrors with a combination logic structure interposing the first and second banks of mirrors. An output data line extends from the first bank of mirrors to the combinational logic structure. An input data line that carries data associated with the second bank of mirrors is also provided to the combinational logic structure. An output data line extends from the combinational logic structure to second data bank.

In one embodiment, a data processing method is for creating write data from design data, and registering the write data into a writing apparatus. The method includes applying, to a plurality of pieces of first frame data into which first chip data of the design data is divided, a plurality of conversion processes to create the write data, and applying a plurality of pre-processes to a plurality of pieces of second frame data into which second chip data of the write data is divided, and registering the second chip data into the writing apparatus. The plurality of conversion processes and the plurality of pre-processes are each performed in a pipeline processing on a per-frame basis. The write data is registered into the writing apparatus on a per-chip basis, on a per-virtual chip basis, or on a per-frame basis. The virtual chip includes a plurality of chips combined together.

The present invention relates to an electron beam (eBeam) resist composition, particularly an (eBeam) resist composition for use in the fabrication of integrated circuits. Such resist compositions include an anti-scattering compound which minimises scattering and secondary electron generation, thus affording extremely high resolution lithography. Such high resolution lithography may be used directly upon silicon-based substrates to produce integrated circuits, or may alternatively be used to produce a lithographic mask (e.g. photomask) to facilitate high-resolution lithography.

In order to solve the problem that information indicating three or more points on a contour of a figure drawn by an electron beam writer cannot be more precisely acquired, an information processing apparatus includes: an accepting unit that accepts pattern information indicating a pattern figure, and actually observed contour information acquired using an image obtained by capturing an image of a figure drawn by an electron beam writer; a transforming information acquiring unit that acquires transforming information, which is information that minimizes the sum of squares of differences between convolution values corresponding to three or more corrected contour points of a given point spread function in a region indicated by the pattern figure indicated by the pattern information and a threshold regarding the convolution values; a corrected contour point acquiring unit that acquires corrected contour point information, which is information indicating three or more corrected contour points respectively corresponding to three or more actually observed contour points, using the transforming information; and an output unit that outputs the corrected contour point information. Accordingly, it is possible to more precisely acquire information indicating three or more points on a contour of a figure drawn by an electron beam writer.

One embodiment relates to an apparatus for aberration correction in an electron beam lithography system. An inner electrode surrounds a pattern generating device, and there is at least one outer electrode around the inner electrode. Each of the inner and outer electrodes has a planar surface in a plane of the pattern generating device. Circuitry is configured to apply an inner voltage level to the inner electrode and at least one outer voltage level to the at least one outer electrode. The voltage levels may be set to correct a curvature of field in the electron beam lithography system. Another embodiment relates to an apparatus for aberration correction used in an electron based system, such as an electron beam inspection, or review, or metrology system. Other embodiments, aspects and features are also disclosed.