The invention relates to a method for electrically examining electronic components of an integrated circuit. According to the invention, a method for electrically examining electronic components of an integrated circuit (1) is provided, comprising a target region (3) to be examined in which electronic components having contact points (5) are located, and a remaining region, referred to as non-target region (2), in which an examination is carried out using a combined SEM/AFM nanoprobe. In a first step, the non-target region (2) is at least partially imaged with the scanning electron microscope part of the SEM/AFM nanoprobe, and in a subsequent step the target region (3) is at least partially imaged with the atomic force microscope part of the SEM/AFM nanoprobe.

In one embodiment, a method includes receiving measured linescan information describing a pattern structure of a feature, applying the received measured linescan information to an inverse linescan model that relates measured linescan information to feature geometry information, and identifying, based at least in part on the applying the received measured linescan model to the inverse linescan model, feature geometry information that describes a feature that would produce a linescan corresponding to the received measured linescan information. The method also includes determining, at least in part using the inverse linescan model, feature edge positions of the identified feature, analyzing the feature edge positions to determine errors in the manufacture of the pattern structure, and controlling a lithography tool based on the analysis of the feature edge positions.

There is provided a system and method of examination of a semiconductor specimen, comprising: obtaining a sequence of frames of an area of the specimen acquired by an electron beam tool configured to scan the area from a plurality of directions, the sequence comprising a plurality of sets of frames each acquired from a respective direction; and registering the plurality of sets of frames and generating an image of the specimen based on result of the registration, comprising: performing, for each direction, a first registration among the set of frames acquired therefrom, and combining the registered set of frames to generate a first composite frame, giving rise to a plurality of first composite frames respectively corresponding to the plurality of directions; and performing a second registration among the plurality of first composite frames, and combining the registered plurality of first composite frames to generate the image of the specimen.

Provided is an inspection apparatus including: an irradiation source irradiating an electron beam to a pattern of an inspection target object, the inspection target object having a first surface and a second surface having the pattern; a first voltage application circuit applying a first voltage to the first surface; a second voltage application circuit applying a second voltage to the second surface; and a detector for acquiring an inspection image generated from the pattern by irradiating the electron beam, wherein |V.sub.acc−V.sub.L|=|V.sub.2|<|V.sub.1| is satisfied, when an acceleration voltage of an electron included in the electron beam is V.sub.acc, an incident voltage of the electron reaching the second surface is denoted by V.sub.L, the first voltage is denoted by V.sub.1, and the second voltage is denoted by V.sub.2.

An improved particle beam inspection apparatus, and more particularly, a particle beam inspection apparatus including a thermal conditioning station for preconditioning a temperature of a wafer is disclosed. The charged particle beam apparatus may scan the wafer to measure one or more characteristics of the structures on the wafer and analyze the one or more characteristics. The charged particle beam apparatus may further determine a temperature characteristic of the wafer based on the analysis of the one or more characteristics of the structure and adjust the thermal conditioning station based on the temperature characteristic.

An inspection apparatus for adjusting a working height for a substrate for multiple target heights is disclosed. The inspection apparatus includes a radiation source configured to provide a radiation beam and a beam splitter configured to split the radiation beam into multiple beamlets that each reflect off a substrate. Each beamlet contains light of multiple wavelengths. The inspection apparatus includes multiple light reflecting components, wherein each light reflecting component is associated with one of the beamlets reflecting off the substrate and is configured to support a different target height for the substrate by detecting a height or a levelness of the substrate based on the beamlet reflecting off the substrate.

According to one embodiment, an electron beam device includes a support which supports the sample and an electrode disposed below the sample on the support The electrode is for applying a voltage to the sample and includes a plurality of columnar electrodes that can be independently controlled to apply different voltages to portions of the sample. A controller for generating correction data for correcting the distribution of an electric field generated across the area of the sample. The correction data is generated based on structure information indicating a structure of the sample. The controller controls the plurality of columnar electrodes to apply local voltages set based on the correction data.

Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

A method of evaluating a region of a sample that includes a plurality of holes, wherein the method includes: taking a first image of the region by scanning the region with a first charged particle beam; evaluating the first image to determine a first center-to-center distance between first and second holes in the plurality of holes; milling a diagonal cut in an area within the region that includes the second hole at an angle such that an upper surface of the sample in the milled area where the second hole is located is recessed with respect to an upper surface of the sample where the first hole is located; thereafter, taking a second image of the region by scanning the region with the first charged particle beam; evaluating the second image to determine a second center-to-center distance between first and second holes in the plurality of holes; and comparing the second center-to-center distance to the first center-to-center distance.

Methods, systems, and computer-readable mediums for configuring a lithography tool to manufacture a semiconductor device. The method includes selecting a first variable, selecting a second variable, selecting at least one response variable that is a function of the first variable and second variable, determining a measurement uncertainty for each response variable, determining, based on a measurement of the response variable, and the measurement uncertainty for the response variable, a plurality of probabilities representing a plurality of indications of whether a plurality of points associated with a lithography process meet a specification requirement for each response variable, wherein the plurality of probabilities represent a process window, and configuring, based on the process window, a lithography tool to manufacture a semiconductor device.