In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

A plasma source array is provided. The plasma source array includes a plurality of hybrid plasma sourcelets disposed on a base plate. Each hybrid sourcelet includes a dielectric tube having an inner area and an outer surface; an inductively coupled plasma source for generating a inductively coupled plasma disposed proximate to the outer surface of the dielectric tube; a capacitively coupled plasma source for generating a capacitively coupled plasma disposed within the inner area of the dielectric tube; and a gas injection system configured to supply one or more process gases to the inner area of the dielectric tube. Plasma processing apparatuses incorporating the plasma source array and methods of use are also provided.

Radio frequency power conveyed to individual process stations of a multi-station integrated circuit fabrication chamber may be adjusted so as to bring the rates at which fabrication processes occur, and/or fabrication process results, into alignment with one another. Such adjustment in radio frequency power, which may be accomplished via adjusting one or more reactive elements of a RF distribution network, may give rise to an imbalance in power delivered to each individual process station.

A fixed outer support flange (flange 1) is formed to circumscribe an electrode within a plasma processing system. Flange 1 has a vertical portion and a horizontal portion extending radially outward from a lower end of the vertical portion. An articulating outer support flange (flange 2) is formed to circumscribe flange 1. Flange 2 has a vertical portion and a horizontal portion extending radially outward from a lower end of the vertical portion. The vertical portion of flange 2 is positioned concentrically outside of the vertical portion of flange 1. Flange 2 is spaced apart from flange 1 and moveable along the vertical portion of flange 1. Each of a plurality of electrically conductive straps has a first end portion connected to flange 2 and a second end portion connected to flange 1.

A plasma treatment chamber comprises one or more sidewalls and a support surface within the sidewalls holds a workpiece. An array of individual gas injectors is distributed about the sidewalls. Pump ports are along the sidewalls to eject gas from the chamber. Aa etch rate uniformity of a material on the workpiece is controlled by: using the array gas injectors to inject one or more gas flows in across the workpiece; injecting a first gas flow from a first set of adjacent individual gas injectors to etch the materials on the workpiece; and simultaneously injecting a second gas flow from remaining gas injectors. The second gas flow either dilutes the first gas flow to reduce an area on the workpiece having a faster etch rate, or acts as an additional etchant to increase the etch rate in the area of the workpiece having the faster etch rate.

Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.

A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.

An edge ring for a substrate processing system includes an annular body and an annular channel disposed in the annular body circumferentially along an inner diameter of the annular body. The annular channel includes N distinct sections, where N is an integer greater than 1. The edge ring includes N injection ports arranged circumferentially on the annular body to respectively inject one or more gases into the N distinct sections of the annular channel. The edge ring includes a flange extending radially inwards from the inner diameter of the annular body. A plurality of slits is arranged in the flange. The slits are in fluid communication with the annular channel and extend radially inwards from the annular channel to deliver the one or more gases.

A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer. In this way, the focus ring provides and/or increases etch rate uniformity across the wafer, which may reduce structural variations across semiconductor devices being formed on the wafer and/or may increase processing yield.

A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.