A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.

Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.

Semiconductor wafers, are processed, using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.

A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.

The present subject matter discloses a method of lateral slicing of cylindrical silicon ingot to maximize resulting chips yield as compared to the conventional transverse slicing of ingot. The resulting rectangular wafers made from lateral slicing of ingot maximizes yield as by the lateral slicing of ingot, overall chips per wafer ratio gets increased as compared to transversal cutting while the said method decreases waste due to conflict between chip and wafer geometry. The novel apparatus or system of present method includes JIG having plurality of parallel bars. The JIG is provided to covers and holds the ingot during slicing while the parallel bars of JIG between which diamond dust embedded wires gets located and which behaves as a guide for diamond embedded wires during the slicing of ingot. Also, this JIG mechanism protects and holds the wires from sliding down and miss the designated location of slicing during the process as the slicing of cylindrical ingot is being done longitudinally. Further, the parallel bars of the JIG mechanism are made such a way that the slurry and debris from the slicing automatically gets released.

A bonded wafer includes: a first wafer having a first surface and a second surface opposite to the first surface, and including a functional element on the first surface; and a second wafer in which a structure having at least one of a hole, a groove and a cavity is formed; wherein an annular protrusion is formed to have a shape to extend along an outer periphery on the second surface of the first wafer; wherein at least a portion of the second wafer is a reduced-diameter portion having a diameter smaller than an inner diameter of the annular protrusion; and wherein, under a state in which the reduced-diameter portion is fitted into a region surrounded by the annular protrusion of the first wafer, the second wafer is bonded to the second surface at least at the region.

A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4 or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm.sup.2 in the epi principal surface.

A semiconductor substrate processing method includes: a peeling layer forming step of forming a peeling layer by irradiating a first semiconductor substrate with a laser beam having a wavelength capable of passing through the first semiconductor substrate while positioning a focal point of the laser beam within the first semiconductor substrate; a second semiconductor substrate forming step of forming a second semiconductor substrate by epitaxial growth on an upper surface of the first semiconductor substrate after performing the peeling layer forming step; a peeling step of peeling off the first semiconductor substrate from the peeling layer; and a grinding step of grinding and removing the first semiconductor substrate after performing the peeling step.

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation 1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.