A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

Provided are: a GaN substrate wafer having a crystallinity suitable as a substrate for a semiconductor device as well as an improved productivity; and a method of producing the same. The GaN substrate wafer is a (0001)-oriented GaN substrate wafer that includes a first region arranged on an N-polar side and a second region arranged on a Ga-polar side via a regrowth interface therebetween. In this GaN substrate wafer, the second region has a minimum thickness of not less than 20 μm, the concentration of at least one element selected from Li, Na, K, F, Cl, Br, and I in the first region is 1×10.sup.15 atoms/cm.sup.3 or higher, and the second region satisfies one or more conditions selected from the following (a) to (c): (a) the Si concentration is 5×10.sup.16 atoms/cm.sup.3 or higher; (b) the O concentration is 3×10.sup.16 atoms/cm.sup.3 or lower; and (c) the H concentration is 1×10.sup.17 atoms/cm.sup.3 or lower.

The present invention provides a method for the formation of graphene on a silicon substrate, the method comprising: (i) providing a silicon wafer having a growth surface which is free of native oxides, in a reaction chamber; (ii) nitriding the growth surface with a nitrogen-containing gas with the wafer at a temperature in excess of 800° C., to thereby form a silicon nitride layer; and (iii) forming a graphene mono-layer or multiple layer structure on the silicon nitride layer; wherein the method is performed in-situ and sequentially in the reaction chamber. The present invention also provides a graphene-on-silicon layer structure having an intervening silicon nitride layer and free of any intervening native oxide layer.

Provided is a GaN substrate wafer with an improved productivity, which can be preferably used in the production of a nitride semiconductor device having a horizontal device structure. The GaN substrate wafer is a (0001)-oriented GaN substrate wafer that includes a first region arranged on an N-polar side and a second region, which is arranged on a Ga-polar side and has a minimum thickness, via a regrowth interface therebetween. In this GaN substrate wafer, the second region has a minimum thickness of not less than 20 μm, and at least a portion of the second region has a total compensating impurity concentration of 1×10.sup.17 atoms/cm.sup.3 or higher.

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.

The method of preparing a silicon carbide ingot includes: disposing a raw material and a silicon carbide seed crystal to be separated in a reactor having an internal space; adjusting a temperature, a pressure, and an atmosphere of the internal space for sublimating the raw material and growing the silicon carbide ingot on the silicon carbide seed crystal; and cooling the reactor and retrieving the silicon carbide ingot, wherein the adjusting proceeds in a first inert gas atmosphere having a flow quantity of 100 sccm to 300 sccm, the cooling proceeds in a second inert gas atmosphere having a flow quantity of 1 sccm to 250 sccm, and the reactor has a thermal conductivity of 120 W/mK or less.

A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

The present invention provides a method for the formation of graphene on a silicon substrate, the method comprising: (i) providing a silicon wafer having a growth surface which is free of native oxides, in a reaction chamber; (ii) nitriding the growth surface with a nitrogen-containing gas with the wafer at a temperature in excess of 800° C., to thereby form a silicon nitride layer; and (iii) forming a graphene mono-layer or multiple layer structure on the silicon nitride layer; wherein the method is performed in-situ and sequentially in the reaction chamber. The present invention also provides a graphene-on-silicon layer structure having an intervening silicon nitride layer and free of any intervening native oxide layer.

A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.