A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.

The invention provides a method for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The method includes rotating a polishing pad, the rotating polishing pad having radial feeder grooves in the polishing layer separating the polishing layer into polishing regions. The polishing regions are circular sectors defined by two adjacent radial feeder grooves. The radial feeder grooves extend from a location adjacent the center to a location adjacent the outer edge. Each polishing region includes a series of biased grooves connecting a pair of adjacent radial feeder grooves. Pressing and rotating the wafer against the rotating polishing pad for multiple rotations of the polishing pad adjusts polishing by either increasing or decreasing residence time of the polishing fluid under the wafer.

The polishing pad is suitable for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The polishing pad includes radial feeder grooves in a polishing layer separating the polishing layer into polishing regions. The radial feeder grooves extend at least from a location adjacent the center to a location adjacent the outer edge of the polishing pad. Each polishing region including a series of biased grooves that connects a pair of adjacent radial feeder grooves. A majority of the biased grooves having either an inward bias toward the center of the polishing pad or an outward bias for directing polishing fluid toward the outer edge of the polishing pad.

The invention provides a method for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The method includes rotating a polishing pad having radial feeder grooves in a polishing layer separating the polishing layer into polishing regions. The radial feeder grooves extend at least from a location adjacent the center to a location adjacent the outer edge. Each polishing region includes a series of biased grooves connecting a pair of adjacent radial feeder grooves. The series of biased grooves separate a land area and have inner walls closer to the center and outer walls closer to the outer edge. Pressing and rotating the wafer against the rotating polishing pad for multiple rotations polishes or planarizes the wafer with land areas wet by the overflowing polishing fluid.

This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

The disclosure herein includes compositions and methods for ionizing targets and methods for making the compositions. In some embodiments, the compositions can include a porous substrate that has been etched for a desired average pore size, a desired porosity, or both for detection of one or more targets of interest. Also disclosed herein are methods for using the composition to ionize targets.