A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure.

A memory circuit includes a memory cell, a first program driver, a second program driver, and a sensing amplifier. A method for operating the memory circuit includes, during a program operation of the memory cell, providing a program voltage to the memory cell, enabling the first program driver to drive the first local bit line to be at a low voltage, enabling the second program driver, disabling the first program driver, and enabling the sensing amplifier to verify whether the first memory cell has been programmed or not. The second program driver has a weaker driving ability than the first program driver.

A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

A substrate processing apparatus comprising a wet processing station with a resist coating device for coating a resist on a substrate and/or a development processing device for developing the resist on the substrate is disclosed. The apparatus may have an additional processing station and a substrate handler for moving the substrate to the wet, and/or additional processing station and moving the substrate in a direction in and/or out of the substrate processing apparatus. The additional processing station comprises an infiltration device.

Provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. The through via is laterally aside the die. The encapsulant laterally encapsulates the through via and the die. The warpage controlling layer covers the encapsulant and the die. The cap is laterally aside the warpage controlling layer and on the through via. The cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.

Provided are nanograting structures and methods of fabrication thereof that allow for stable, robust gratings and nanostructure embedded gratings that enhance electromagnetic field, fluorescence, and photothermal coupling through surface plasmon or, photonic resonance. The gratings produced exhibit long term stability of the grating structure and improved shelf life without degradation of the properties such as fluorescence enhancement. Embodiments of the invention build nanograting structures layer-by-layer to optimize structural and optical properties and to enhance durability.

A composite structure, intended for a planar co-integration of electronic components of different functions, the composite structure including from its base towards its surface: a support substrate made of a first material, the support substrate including cavities each opening into an upper face of the support substrate, the cavities being filled with at least one composite material consisting of a matrix of a crosslinked preceramic polymer, the matrix being charged with inorganic particles; and a thin film made of a second material, the thin film being bonded to the upper face of the support substrate and to the composite material.

A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.