The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

A method for producing a semiconductor device includes the steps of: providing a substrate product including a substrate and a first stacked semiconductor layer disposed on the substrate, the first stacked semiconductor layer including a plurality of semiconductor layers having different compositions that are alternately and periodically stacked with a predetermined period; forming a mask on the substrate product; and etching the first stacked semiconductor layer using the mask. The step of etching the first stacked semiconductor layer includes the steps of: optically monitoring an optical signal including a light component reflected from an etched surface of the substrate product for detecting an endpoint of etching; converting the optical signal to an electric signal to generate a monitoring signal; performing Fourier transform on the monitoring signal to generate a spectrum signal; and determining the endpoint detection of the etching by using the spectrum signal provided by the Fourier transform.

A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550 C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

Provided are nanograting structures and methods of fabrication thereof that allow for stable, robust gratings and nanostructure embedded gratings that enhance electromagnetic field, fluorescence, and photothermal coupling through surface plasmon or, photonic resonance. The gratings produced exhibit long term stability of the grating structure and improved shelf life without degradation of the properties such as fluorescence enhancement. Embodiments of the invention build nanograting structures layer-by-layer to optimize structural and optical properties and to enhance durability.

A system and method for depositing a metal dielectric film includes arranging a substrate in a plasma enhanced chemical vapor deposition (PECVD) processing chamber; supplying a carrier gas to the PECVD processing chamber; supplying a dielectric precursor gas to the PECVD processing chamber; supplying a metal precursor gas to the PECVD processing chamber; creating plasma in the PECVD processing chamber; and depositing a metal dielectric film on the substrate at a process temperature that is less than 500 C.

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.