A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.

A memory circuit includes a memory cell, a first program driver, a second program driver, and a sensing amplifier. A method for operating the memory circuit includes, during a program operation of the memory cell, providing a program voltage to the memory cell, enabling the first program driver to drive the first local bit line to be at a low voltage, enabling the second program driver, disabling the first program driver, and enabling the sensing amplifier to verify whether the first memory cell has been programmed or not. The second program driver has a weaker driving ability than the first program driver.

A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

The disclosure provides a liquid crystal display panel, an array substrate and a manufacturing method thereof. In the method, controllable resistance spacer layers are formed on at least one of a source doped region and a drain doped region of a low temperature polysilicon active layer. When a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current; and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current, such that contact regions formed of the controllable resistance spacer layers are respectively connected with the corresponding source layer and the corresponding drain through the controllable resistance spacer layers. Therefore, the disclosure is capable of effectively decreasing a leakage of a thin film transistor.

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800 C. to about 950 C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

Methods for removing a passivation film from a copper surface can include exposing the passivation film to a vapor phase organic reactant, for example at a temperature of 100 C. to 400 C. In some embodiments, the passivation film may have been formed by exposure of the copper surface to benzotriazole, such as can occur during a chemical mechanical planarization process. The methods can be performed as part of a process for integrated circuit fabrication. A second material can be selectively deposited on the cleaned copper surface relative to another surface of the substrate.

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.