A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm.Math.cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800 C. and 1250 C. and then cooled at a cooldown rate less than 5 C./second when the curing temperature is between 1250 C. and 1150 C., less than 20 C./second when the curing temperature is between 1150 C. and 1100 C., and less than 50 C./second when the curing temperature is between 1100 C. and 800 C.

Representative systems and methods for preventing or otherwise reducing extreme-ultraviolet-induced material property changes (e.g., layer thickness shrinkage) include one or more thermal treatments to at least partially stabilize a material forming a material layer disposed over a substrate prior to extreme ultraviolet (EUV) exposure (e.g., wavelengths spanning about 124 nm to about 10 nm) attendant to photolithographic processing. Representative systems and methods provide for reduction of average compressive stress in a material layer after thermal treatment prior to extreme EUV photolithographic patterning. Representative thermal treatments may include one or more annealing processes, ultraviolet (UV) radiation treatments, ion implantations, ion bombardments, plasma treatments, surface baking treatments, surface coating treatments, surface ashing treatments, or pulsed laser treatments.

A method for manufacturing a semiconductor device includes forming a plurality of amorphous silicon germanium (a-SiGe) structures having a first percentage of germanium on a substrate, forming a plurality of spacers on sides of the plurality of a-SiGe structures, performing an annealing to convert a portion of each of the a-SiGe structures into respective portions comprising a-SiGe having a second percentage of germanium higher than the first percentage of germanium, and to convert each of the spacers into respective silicon oxide portions, removing from the substrate at least one of: one or more unconverted portions of the a-SiGe structures having the first percentage of germanium, one or more of the converted portions of a-SiGe structures, and one or more of the silicon oxide portions, and transferring a pattern to the substrate to form a plurality of patterned substrate portions, wherein the pattern includes the portions remaining after the removing.

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

A method for manufacturing a substrate is disclosed. The method comprises the following steps: step one, depositing an amorphous silicon layer on a base material; step two, depositing a silicon dioxide layer with a first thickness on the amorphous silicon layer; and step three, etching the silicon dioxide layer until a thickness thereof is reduced to a second thickness. According to the method of the present disclosure, the silicon dioxide layer with a needed thickness can be manufactured on the amorphous silicon layer. When the ELA procedure is performed, the silicon dioxide layer has an enough thickness to prevent the formation of protrusions at grain boundary of polysilicon, so that the semi-conductive layer manufactured therein can have a relatively low roughness.

A manufacturing method for a light emitting device, a light emitting device, and a hybrid light emitting device, the manufacturing method comprises the following steps: step S1: disposing a mask plate having a plurality of hollow portions on a substrate; step S2: by using a solution method, applying ink on a surface of the substrate through the hollow portions; and step S3: drying or solidifying the ink on the surface of the substrate to form a light emitting layer or a functional layer.

A method for manufacturing a semiconductor device includes forming a plurality of amorphous silicon germanium (a-SiGe) structures having a first percentage of germanium on a substrate, forming a plurality of spacers on sides of the plurality of a-SiGe structures, performing an annealing to convert a portion of each of the a-SiGe structures into respective portions comprising a-SiGe having a second percentage of germanium higher than the first percentage of germanium, and to convert each of the spacers into respective silicon oxide portions, removing from the substrate at least one of: one or more unconverted portions of the a-SiGe structures having the first percentage of germanium, one or more of the converted portions of a-SiGe structures, and one or more of the silicon oxide portions, and transferring a pattern to the substrate to form a plurality of patterned substrate portions, wherein the pattern includes the portions remaining after the removing.

A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.