A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm.Math.cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800 C. and 1250 C. and then cooled at a cooldown rate less than 5 C./second when the curing temperature is between 1250 C. and 1150 C., less than 20 C./second when the curing temperature is between 1150 C. and 1100 C., and less than 50 C./second when the curing temperature is between 1100 C. and 800 C.

Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

A structure is provided that comprises a substrate, a plurality of elements, and a plurality of trenches disposed on the substrate. Each element is separated from adjacent elements by a trench in the plurality of trenches and has a top surface with a first and an opposing second side. A first portion of the top surface is on the first side and a second portion of the top surface is on the opposing second side. The structure further comprises a plurality of first graphene layers, each of which is formed on the first portion of the top surface of an element in the plurality of elements. The structure further comprises a plurality of second graphene layers, each of which is formed on the second portion of the top surface of a corresponding element so that each element is separately overlayed by a first graphene layer and a second graphene layer.

A method of forming a graphite-based structure on a substrate comprises patterning the substrate thereby forming a plurality of elements on the substrate. Each respective element in the plurality of elements is separated from an adjacent element on the substrate by a corresponding trench in a plurality of trenches on the substrate and each respective element in the plurality of elements has a corresponding top surface. The method further comprises segmentedly depositing a graphene initiating layer onto the top surface of each respective element in the plurality of elements; and generating graphene using the graphene initiating layer thereby forming the graphite-based structure.

Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.