Patent classifications
H01L21/02436
Method for manufacturing magnetoresistive element
Provided is a method for manufacturing a magnetoresistive element, including a step of forming a tunnel barrier layer, wherein the step of forming the tunnel barrier layer includes a deposition step of depositing a metal film on top of a substrate, and an oxidation step of subjecting the metal film to an oxidation process. The oxidation step includes holding the substrate having Mg formed thereon, on a substrate holder in a processing container in which the oxidation process is performed, supplying an oxygen gas to the substrate by introducing the oxygen gas into the processing container, at a temperature at which Mg does not sublime, and heating the substrate after the introduction of the oxygen gas.
INTEGRATION OF III-V COMPOUND MATERIALS ON SILICON
A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.
Method for forming low temperature polysilicon thin film
Embodiments of the present invention provide a method for forming a low temperature polysilicon thin film. The method for forming the low temperature polysilicon thin film can include: depositing a buffer layer and an amorphous silicon layer on a substrate in this order; heating the amorphous silicon layer; performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer; oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; and removing the oxidation portion of the polysilicon layer to form a polysilicon thin film.
Formation of single crystal semiconductors using planar vapor liquid solid epitaxy
A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.
Method for manufacturing a substrate
A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
Epitaxial structure of semiconductor device and method of manufacturing the same
Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.