A method for manufacturing a graphite layer on an interstitial carbide layer, includes depositing a metal layer formed by one or more metals on a carbide substrate, the metal layer being able to form an interstitial carbide, the metal layer at least partially covering the carbide substrate; performing a heat treatment during which a temperature higher than the dissociation temperature of the carbide of the carbide substrate is applied; wherein the heat allows a reaction between the metal layer and the carbide substrate to form the interstitial carbide layer as well as a first part of the graphite layer at the surface of the interstitial carbide layer, and, when the metal layer only partially covers the carbide substrate, a formation of a second part of the graphite layer at the surface of the carbide substrate which is not covered with the metal layer.

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

The present invention relates to methods for fabricating vertical homogenous and heterogeneous two-dimensional structures, the fabricated vertical two-dimensional structures, and methods of using the same. The methods demonstrated herein produce structures that are free standing and electrically isolated.

There is provided a SiC film forming method for forming a SiC film on a workpiece, including: a first step of forming a carbon film on the workpiece; and a second step of exposing the carbon film to a silicon-containing gas and causing silicon to be combined into the carbon film.

A silicon carbide (SiC) structure and a method of forming the SiC structure are disclosed. The SiC structure includes an SiC substrate and a film provided on the SiC substrate. The SiC substrate contains both of a hexagonal close packed (hcp) structure and a face centered cubic (fcc) structure, and has only one of the hcp surface and the fcc surface, where the hcp surface includes atoms in the topmost layer whose rows overlap with rows of atoms in the third layer, while, the fcc surface includes atoms in the topmost layer whose rows are different from rows of atoms in the third layer.

Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

A method for producing an electronic device involves forming a graphene precursor on a first portion of a common semiconductor substrate, forming a graphene layer on the graphene precursor, and forming a semiconductor device on a second portion of the common semiconductor substrate.

A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.

In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.