H01L21/02612

Solid phase epitaxy of 3C—SiC on Si(001)

A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3CSiC buffer layer on Si(001) comprising a porous buffer layer of 3CSiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.

Fin isolation structures facilitating different fin isolation schemes

Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

LAYERED BODY AND ELECTRONIC ELEMENT

A laminated body includes: a substrate portion composed of silicon carbide; and a graphene film disposed on a first main surface of the substrate portion, the graphene film having an atomic arrangement oriented with respect to an atomic arrangement of the silicon carbide of the substrate portion. A region in which a value of G/G in Raman spectrometry is not less than 1.2 is not less than 10% in an area ratio in an exposed surface of the graphene film, the exposed surface being a main surface of the graphene film opposite to the substrate portion.

METHOD FOR FORMING A SEMICONDUCTING PORTION BY EPITAXIAL GROWTH ON A STRAINED PORTION

The invention pertains to formation of a semiconducting portion (60) by epitaxial growth on a strained germination portion (40), comprising the steps in which a cavity (21) is produced under a structured part (11) by rendering free a support layer (30) situated facing the structured part (11), a central portion (40), termed the strained germination portion, then being strained; and a semiconducting portion (60) is formed by epitaxial growth on the strained germination portion (40), wherein the structured part (11) is furthermore placed in contact with the support layer (30) in such a way as to bind the structured part (11) of the support layer.

Formation of germanium-containing channel region by thermal condensation utilizing an oxygen permeable material

A structure including a first semiconductor material portion and a second semiconductor material portion is provided. An oxygen impermeable hard mask is then formed directly on a surface of the first semiconductor material portion. Next, a silicon germanium layer is epitaxially formed on the second semiconductor material portion, but not the first semiconductor material portion. An oxygen permeable hard mask is then formed over the first and second semiconductor material portions. A thermal condensation process is then performed which converts the second semiconductor material portion into a germanium-containing semiconductor material portion. The oxygen permeable hard mask and the oxygen impermeable hard mask are then removed. A functional gate structure can be formed atop the remaining first semiconductor material portion and the thus formed germanium-containing semiconductor material portion.

SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS
20170053796 · 2017-02-23 ·

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

SEMICONDUCTOR STRUCTURE WITH A SILICON GERMANIUM ALLOY FIN AND SILICON GERMANIUM ALLOY PAD STRUCTURE

A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.

GRAPHENE AND HEXAGONAL BORON NITRIDE PLANES AND ASSOCIATED METHODS

Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

Process for working a wafer of 4H—SiC material to form a 3C—SiC layer in direct contact with the 4H—SiC material

Process for manufacturing a 3CSiC layer, comprising the steps of: providing a wafer of 4HSiC, provided with a surface; heating, through a LASER beam, a selective portion of the wafer at least up to a melting temperature of the material of the selective portion; allowing the cooling and crystallization of the melted selective portion, thus forming the 3CSiC layer, a Silicon layer on the 3CSiC layer and a carbon-rich layer above the Silicon layer; completely removing the carbon-rich layer and the Silicon layer, exposing the 3CSiC layer. If the Silicon layer is maintained on the 4HSiC wafer, the process leads to the formation of a Silicon layer on the 4HSiC wafer. The 3CSiC or Silicon layer thus formed may be used for the integration, even only partial, of electrical or electronic components.

Method of growing monolayer transition metal dichalcogenides via sulfurization and subsequent sublimation

A method for forming a transition metal dichalcogenide monolayer, which includes depositing a transition metal, a transition metal oxide, or a mixture thereof, on a substrate, introducing a chalcogen precursor to the transition metal, the transition metal oxide, or the mixture thereof, in the presence of an etching gas and a carrier gas at a first temperature, to form a transition metal dichalcogenide on the substrate from the transition metal, the transition metal oxide, or the mixture thereof, and subliming the transition metal dichalcogenide on the substrate in the presence of a pulsating supply of a vapor of the chalcogen precursor to form the transition metal dichalcogenide monolayer at a second temperature, wherein the vapor of the chalcogen precursor comprises a chalcogen vapor.